LTC2233 Linear Technology, LTC2233 Datasheet - Page 22

• Manufacturer Part Number: LTC2233
• Description: 10-Bit 105Msps/80Msps ADCs
• Manufacturer: Linear Technology

LTC2232/LTC2233
APPLICATIO S I FOR ATIO
Data Format
The LTC2232/LTC2233 parallel digital output can be se-
lected for offset binary or 2’s complement format. The
format is selected with the MODE pin. Connecting MODE
to GND or 1/3V
Connecting MODE to 2/3V
ment output format. An external resistor divider can be
used to set the 1/3V
shows the logic states for the MODE pin.
22
Table 2. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. Data will be
updated just after CLKOUT rises and can be latched on the
falling edge of CLKOUT.
DD
DD
DD
2’s Complement
2’s Complement
Output Format
DD
Offset Binary
Offset Binary
U
selects offset binary output format.
DD
or 2/3V
U
DD
or V
DD
DD
W
logic values. Table 2
selects 2’s comple-
Cycle Stablizer
Clock Duty
+
Off
Off
On
On
input available
U
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV
OV
can be powered with any voltage from GND up to 1V and
must be less than OV
tween OGND and OV
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF and CLKOUT.
The data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
DD
can be powered with any voltage up to 3.6V. OGND
DD
should be tied to that same 1.8V supply.
DD
DD
.
. The logic outputs will swing be-
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DD
DD
, should be tied
and OE to V
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DD