LTC2233 Linear Technology, LTC2233 Datasheet - Page 21

• Manufacturer Part Number: LTC2233
• Description: 10-Bit 105Msps/80Msps ADCs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
The lower limit of the LTC2232/LTC2233 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2232/LTC2233 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
>+1.000000V
<–1.000000V
A
(2V Range)
+0.998047V
+0.996094V
+0.001953V
–0.001953V
–0.003906V
–0.998047V
–1.000000V
0.000000V
IN
+
Figure 12b. ENC Drive Using a CMOS to PECL Translator
– A
IN
MC100LVELT22
–
V
THRESHOLD
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
OF
0
0
0
0
0
0
0
1
0
1
D0
= 1.6V
U
3.3V
(Offset Binary)
11 1111 1111
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
00 0000 0000
Q0
Q0
D9 – D0
0.1µF
U
130Ω
83Ω
1.6V
3.3V
ENC
ENC
W
ENC
ENC
+
–
130Ω
83Ω
+
–
LTC2232/
LTC2233
(2’s Complement)
LTC2232/
LTC2233
22323 F12a
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
10 0000 0000
D9 – D0
22323 F12b
U
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional N-
channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2232/LTC2233 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
from the digital outputs.
LATCH
FROM
DATA
OE
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
Figure 13. Digital Output Buffer
LTC2232/LTC2233
V
DD
www.DataSheet4U.com
LTC2232/LTC2233
OV
DD
DD
and OGND, iso-
43Ω
22323 F13
OV
OGND
DD
21
TYPICAL
DATA
OUTPUT
22323fa
0.5V
TO 3.6V
0.1µF