LTC2223 Linear Technology, LTC2223 Datasheet - Page 21

• Manufacturer Part Number: LTC2223
• Description: (LTC2222 / LTC2223) 105Msps/80Msps ADCs
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
The lower limit of the LTC2222/LTC2223 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2222/LTC2223 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
>+1.000000V
<–1.000000V
A
(2V Range)
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
0.000000V
IN
Figure 12b. ENC Drive Using a CMOS to PECL Translator
+
– A
IN
MC100LVELT22
–
Figure 12a. Single-Ended ENC Drive,
V
THRESHOLD
Not Recommended for Low Jitter
OF
D0
1
0
0
0
0
0
0
0
0
1
U
3.3V
= 1.6V
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
(Offset Binary)
Q0
Q0
130Ω
D11 – D0
U
83Ω
0.1µF
3.3V
1.6V
ENC
ENC
ENC
ENC
130Ω
83Ω
W
+
–
+
–
LTC2222/
LTC2222/
LTC2223
LTC2223
(2’s Complement)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
22223 F09b
22223 F09a
D11 – D0
U
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2222/LTC2223 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
from the digital outputs.
LATCH
FROM
DATA
OE
PREDRIVER
DD
LOGIC
V
DD
voltages will also help reduce interference
Figure 13. Digital Output Buffer
LTC2222/LTC2223
V
DD
LTC2222/LTC2223
OV
DD
DD
and OGND, iso-
43Ω
22223 F13
OV
OGND
DD
21
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
0.1µF
22223fa