LTC1856 Linear Technology, LTC1856 Datasheet - Page 16

• Manufacturer Part Number: LTC1856
• Description: 100ksps ADC Converters
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
LTC1854/LTC1855/LTC1856
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where a
DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution of
output code is shown for a DC input that has been digitized
4096 times. The distribution is Gaussian and the RMS
code transition is about 1LSB for the LTC1856.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4ms. No external adjustments
are required and, with the maximum acquisition time of 4ms,
throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1854/LTC1855/LTC1856 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1854/LTC1855/LTC1856 recognize 3V or
5V inputs. The LTC1854/LTC1855/LTC1856 have a dedi-
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Figure 5. LTC1856 Histogram for 4096 Conversions
1800
1600
1400
1200
1000
800
600
400
200
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cated output supply pin (OV
swings of the digital output pins (SDO, BUSY) and allows
the part to interface to either 3V or 5V digital systems. The
SDO output is two’s complement.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CONVST and RD. To start a conversion and
put the sample-and-hold into the hold mode bring CONVST
high for at least 40ns. Once initiated it cannot be restarted
until the conversion is complete. Converter status is
indicated by the BUSY output, which goes low while the
conversion is in progress.
Figures 6a and 6b show two different modes of operation
for the LTC1856. For the 12-bit LTC1854 and 14-bit
LTC1855, the last four and two bits of the SDO will output
zeros, respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output is
available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
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