LTC1856 Linear Technology, LTC1856 Datasheet - Page 13

• Manufacturer Part Number: LTC1856
• Description: 100ksps ADC Converters
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
OVERVIEW
The LTC1854/LTC1855/LTC1856 are innovative, multi-
channel ADCs. The on-chip resistors provide attenuation
and offset for each channel. The precisely trimmed attenu-
ators ensure an accurate input range. Because they pre-
cede the multiplexer, errors due to multiplexer
on-resistance are eliminated.
The input word selects the single ended or differential
inputs for each channel or pair of channels. Overrange
protection is provided for unselected channels. An
overrange condition on an unused channel will not affect
the conversion result on the selected channel.
CONVERSION DETAILS
The LTC1854/LTC1855/LTC1856 use a successive approxi-
mation algorithm and an internal sample-and-hold circuit
to convert an analog signal to a 12-/14-/16-bit serial out-
put respectively. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
The analog signals applied at the MUX input channels are
rescaled by the resistor divider network formed by R1, R2
and R3 as shown below. The rescaled signals appear on
the MUXOUT (Pins 10, 11) which are also connected to the
ADC inputs (Pins 12, 13) under normal operation.
INPUT
MUX
U
25k
R1
U
10k
REFCOMP
R3
R2
17k
CH SEL
W
MUXOUT
18545
AI01
U
Before starting a conversion, an 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges to
select the MUX address and power down mode. The ADC
enters acquisition mode on the falling edge of the sixth
clock in the 8-bit data word and ends on the rising edge of
the CONVST signal which also starts a conversion (see
Figure 7). A minimum time of 4ms will provide enough time
for the sample-and-hold capacitors to acquire the analog
signal. Once a conversion cycle has begun, it cannot be
restarted.
During the conversion, the internal differential 12-/14-/16-
bit capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a high speed comparator.
At the end of a conversion, the DAC output balances the
analog input (ADC
/16-bit data word) which represents the difference of ADC
and ADC
DRIVING THE ANALOG INPUTS
The input range for the LTC1854/LTC1855/LTC1856 is
±10V and the MUX inputs are overvoltage protected to
±30V. The input impedance is typically 31kW; therefore, it
should be driven with a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 3000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
taken to select an amplifier with adequate accuracy, linear-
ity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1854/LTC1855/LTC1856. More detailed information
is available in the Linear Technology data books and online
at www.linear.com.
LT
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
®
1007: Low noise precision amplifier. 2.7mA supply
LTC1854/LTC1855/LTC1856
–
are loaded into the 12-/14-/16-bit shift register.
+
– ADC
–
). The SAR contents (a 12-/14-
13
185456fa
+