LTC1743 Linear Technology, LTC1743 Datasheet - Page 14

• Manufacturer Part Number: LTC1743
• Description: 12-Bit 50Msps ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1743
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
a common mode voltage of 2.5V. The V
(Pin 2) may be used to provide the common mode bias
level. V
former to set the DC input level or as a reference level to
an op amp differential driver circuit. The V
bypassed to ground close to the ADC with 4.7 F or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1743 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 7pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1 / (2F
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100
14
0.8V for the 3.2V range or 0.5V for the 2V range, around
CM
can be tied directly to the center tap of a trans-
U
U
or less for each input. The
W
encode
CM
CM
pin must be
); however,
output pin
U
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1743 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
for each ADC input. A disadvantage of using a
ANALOG
INPUT
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
0.1 F
100
1:1
100
37
37
CM
www.DataSheet4U.com
, setting the ADC input
18pF
4.7 F
18pF
18pF
V
A
A
CM
IN
IN
+
–
LTC1743
1743 F03
1743f