LTC1735I-1 Linear Technology, LTC1735I-1 Datasheet - Page 24

• Manufacturer Part Number: LTC1735I-1
• Description: High Efficiency Synchronous Step-Down Switching Regulator
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1735-1
Design Example
As a design example, assume V
22V (max), V
R
Assume a 1.2 H inductor and check the actual value of the
ripple current. The following equation is used :
The highest value of the ripple current occurs at the
maximum input and output voltages:
The maximum ripple current is 32% of maximum output
current, which is about right.
Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V
mum V
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
in; R
voltage with T(estimated) = 50 C:
Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral-
leled. Choosing Fairchild FDS6680A MOSFETs yields a
parallel R
for both bottom MOSFETs, again assuming T = 50 C, is:
24
P
MAIN
SENSE
R
C
t
ON MIN
OSC
SENSE
I
I
DS(ON)
L
L
(
OUT
and C
= 1.61(10
568
1 5
22
DS(ON)
V
300
( )( )
.
= 50mV/12A = 0.042
)
f L
1 7 22
.
OUT
V
.
= 0.03 , C
V
mW
OSC
kHz
OUT
V
1 5
12 1 0 005 50
IN MAX
.
V
of 0.0065 . The total power dissipation
– 1
(
( .
OUT
V
can immediately be calculated:
7
V
1 2
= 1.5V, I
2
)/(300kHz) – 11pF = 43pF
U
2
V
V
OUT
12
)
IN
H
f
RSS
( .
)
A
U
1
22 300
MAX
–
80
= 80pF. At maximum input
V
1 5
22
pF
)(
1 5
(
IN
.
= 12A and f = 300kHz,
.
V
V
= 12V (nominal), V
V
300
W
kHz
C
–
kHz
3 9
)
25
.
A
227
C
IN
)
U
and mini-
ns
0 03
.
IN
=
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short circuit will be less than under full-load
conditions.
C
temperature. C
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
Since the output voltage is below 2.4V, the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an
output voltage of 1.512V.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735-1. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1. Are the signal and power grounds segregated? The
2. Does the V
IN
V
LTC1735-1 PGND pin should tie to the ground plane
close to the input capacitor(s). The SGND pin should
then connect to PGND and all components that connect
to SGND should make a single-point tie to the SGND
pin. The synchronous MOSFET source should connect
to the input capacitor(s) ground.
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C
The 47pF capacitor from V
as close as possible to the LTC1735-1. Be careful
locating the feedback resistors too far away from the
P
R MAX
is chosen for an RMS current rating of at least 6A at
SYNC
ORIPPLE
1
(
)
959
22
= R
OSENSE
V
OUT
24
ESR
22
mW
– .
k
V
1 5
is chosen with an ESR of 0.01 for low
( I
2 4
pin connect directly to the feedback
V
.
L
) = 0.01 (3.9A) = 39mV
V
0 8
12
.
– .
A
V
1 5
OSENSE
2
V
1 1 0 0065
.
OUT
21 3
to SGND should be
.
and signal ground.
.
k
P-P