LTC1735I-1 Linear Technology, LTC1735I-1 Datasheet - Page 18

• Manufacturer Part Number: LTC1735I-1
• Description: High Efficiency Synchronous Step-Down Switching Regulator
• Manufacturer: Linear Technology

LTC1735-1
APPLICATIO S I FOR ATIO
Minimum On-Time Considerations
Minimum on-time t
that the LTC1735-1 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1735-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC1735-1 in a properly
configured application is less than 200ns. However, as the
peak sense voltage decreases, the minimum on-time
gradually increases as shown in Figure 6. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini-
mum on-time requirement. As a general rule keep the
inductor ripple current equal or greater than 30% of
I
18
OUT(MAX)
t
ON MIN
(
at V
250
200
150
100
)
50
0
0
Figure 6. Minimum On-Time vs I
IN(MAX)
V
V f
IN
OUT
( )
ON(MIN)
U
10
.
I
L
/I
OUT(MAX)
U
is the smallest amount of time
20
(%)
30
W
1736-1 F06
40
L
U
PGOOD Pin Operation
The PGOOD pin is a multifunction pin intended primarily to
indicate when the output voltage is within 7.5% of its
nominal set point. A window comparator monitors the
V
that pulls down the PGOOD pin when the output voltage is
out of regulation. Normally a 10k to 100k pull-up resistor
is connected to this pin from a voltage source such as
INT
pin. Dynamically changing the output voltage between two
voltage levels greater that 7.5% apart from each other will
invoke the power good indication, causing the PGOOD
output to go low until the new output voltage is reached.
When the DC voltage on the PGOOD pin drops below its
0.8V threshold, continuous mode operation is forced. In
this case, the top and bottom MOSFETs continue to be
driven synchronously regardless of the load on the main
output. Burst Mode operation is disabled and current
reversal is allowed in the inductor. This mode is forced
whenever the output voltage is not within its 7.5%
window.
In addition to providing a power good output, the PGOOD
pin provides a logic input to force continuous synchro-
nous operation and allow synchronization to an external
clock.
The internal LTC1735-1 oscillator can be synchronized to
an external oscillator by applying a clock signal to the
PGOOD pin though a series resistor with a signal ampli-
tude above 1.5V
frequency, Burst Mode operation is disabled but cycle
skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap capacitor is kept
refreshed. The rising edge of an external clock applied to
the PGOOD pin starts a new cycle. If the output voltage is
not within the 7.5% window around its nominal set point,
the open-drain PGOOD output will pull low, disabling the
external synchronization.
The following table summarizes the possible states avail-
able on the PGOOD pin.
OSENSE
VCC
. Do not apply a voltage greater than INTV
pin and activates an open-drain internal MOSFET
P-P
. When synchronized to an external
CC
to this