LTC1592 Linear Integrated Systems, LTC1592 Datasheet - Page 7

• Manufacturer Part Number: LTC1592
• Description: (LTC1588 - LTC1592) 12-/14-/16-Bit SoftSpan DACs
• Manufacturer: Linear Integrated Systems

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FU CTIO TABLE
I
inverting input of the current-to-voltage op amp.
I
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog
ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground
plane.
V
Requires a 0.1 F bypass capacitor to ground.
SDO (Pin 10): Serial Data Output. Data at this pin is shifted
out on the rising edge of SCK.
SDI (Pin 11): Serial Data Input.
PI FU CTIO S
Table 1
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
OUT1
OUT2
C3
CC
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
U
U
COMMAND
(Pin 9): Positive Supply Input. 4.5V
C2
(Pin 6): Complement of DAC Current Output. Nor-
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(Pin 5): True DAC Current Output. Tied to the
C1
U
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
U
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Copy Data Word Dn in SReg to Buf1
Copy the Data in Buf1 to Buf2
Copy Data Word Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 2.5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
No Operation
U
ON THE RISING EDGE OF CS/LD
EACH COMMAND IS EXECUTED
OPERATION
V
CC
5.5V.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
is shifted into the input shift register on rising edge of SCK.
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCK is enabled for shifting data into the input shift register.
When CS/LD is pulled high, SCK is disabled and the control
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to 15V.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
reference input REF (Pin 15) and the output of the inverting
amplifier tied to R
LTC1588/LTC1589/LTC1592
SHIFT REGISTER
DATA WORD
Dn IN INPUT
SREG
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
X
X
COM
Internal Register Status
No Change
(Pin 1).
BUFFER
INPUT
BUF1
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
(DAC OUTPUT)
No Change
No Change
BUFFER
BUF2
DAC
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
–2.5V to 7.5V
No Change
No Change
No Change
No Change
OUTPUT
RANGE
DAC
10V
2.5V
5V
10V
5V
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