LTC1592 Linear Integrated Systems, LTC1592 Datasheet - Page 4

• Manufacturer Part Number: LTC1592
• Description: (LTC1588 - LTC1592) 12-/14-/16-Bit SoftSpan DACs
• Manufacturer: Linear Integrated Systems

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TYPICAL PERFOR A CE CHARACTERISTICS
LTC1588/LTC1589/LTC1592
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are T
SYMBOL PARAMETER
Power Supply
V
I
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: 1LSB = 0.0015% of full scale = 15.3ppm of full scale
(LTC1592). 1LSB = 0.006% of full scale = 61.2ppm of full scale
(LTC1589). 1LSB = 0.024% of full scale = 244.8ppm of full scale
(LTC1588).
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: I
Note 6: Typical temperature coefficient is 100ppm/ C.
Note 7: To 0.0015% for a full-scale change, measured from the falling
edge of LD for the LTC1592 only.
Note 8: REF = 6V
amplifier = LT1468.
4
CC
CC
–20
– 40
–10
– 30
40
30
20
10
0
Midscale Glitch Impulse
0
USING AN LT1468
C
V
OUT1
FEEDBACK
REF
Supply Voltage
Supply Current, V
= 10V
with DAC register loaded to all 0s.
0.2
RMS
= 30pF
1nV-s TYPICAL
at 1kHz. DAC register loaded with all 1s. Output
0.4
TIME ( s)
CC
0.6
W
0.8
1588992 G03
U
1.0
CONDITIONS
Digital Inputs = 0V or V
A
5
4
1
3
2
0
= T
Supply Current vs Input Voltage
0
V
ALL DIGITAL INPUTS
TIED TOGETHER
MIN
CC
= 5V
to T
The
1
CC
MAX
INPUT VOLTAGE (V)
denotes specifications which apply over the full operating
, V
2
CC
Note 9: Calculation from e
(1.38E-23 J/ K); R = resistance ( ); T = temperature ( K); B = bandwidth
(Hz).
Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.
Note 11: R1 and R2 are measured between R1 and R
Note 12: If a continuous clock is used with data changing on the rising
edge of SCK, setup and hold time (t
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).
Note 13: SDO propagation delay and SDI setup time (t
maximum clock frequency for daisy chaining.
= 5V, V
3
REF
4
(LTC1588/LTC1589/LTC1592)
1588992 G09
= 5V, I
5
OUT2
n
= 4kTRB where: k = Boltzmann constant
= AGND = GND = 0V.
3.0
2.5
0.5
2.0
1.5
1.0
0
0
Logic Threshold vs Supply Voltage
MIN
1
4.5
, t
2
) will limit the maximum clock
1
SUPPLY VOLTAGE (V)
2
TYP
5
3
COM
8
, t
MAX
, R2 and R
5.5
1
4
10
) limit the
5
1588992fa
COM
1588992 G10
6
UNITS
.
V
A
7