LTC1412 Linear Technology, LTC1412 Datasheet - Page 7

• Manufacturer Part Number: LTC1412
• Description: 12-Bit/ 3Msps/ Sampling A/D Converter
• Manufacturer: Linear Technology

FUNCTIONAL BLOCK DIAGRA
APPLICATIONS
TEST CIRCUITS
Conversion Details
The LTC1412 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
DBN
U
A) HI-Z TO V
1k
OH
REFCOMP
U
Load Circuits for Access Timing
AND V
(4.06V)
AGND
DGND
V
A
A
REF
IN
IN
OL
+
–
U
TO V
OH
C
L
INFORMATION
U
2k
DBN
B) HI-Z TO V
REF AMP
W
2.5V REF
INTERNAL
CLOCK
OL
5V
AND V
1k
C
L
OH
U
W
TO V
1412 TC01
SUCCESSIVE APPROXIMATION
OL
12-BIT CAPACITIVE DAC
CONVST
CONTROL LOGIC
C
C
SAMPLE
SAMPLE
REGISTER
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the A
connected to the sample-and-hold capacitors (C
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 50ns will provide enough time for the
CS
DBN
A) V
Load Circuits for Output Float Delay
BUSY
1k
OH
ZEROING SWITCHES
+
–
TO HI-Z
12
COMP
LATCHES
OUTPUT
100pF
1412 BD
IN
DBN
+
•
•
•
and A
D11
D0
OV
OGND
AV
DV
B) V
DD
DD
DD
LTC1412
OL
IN
5V
TO HI-Z
–
1k
1412 TC02
100pF
inputs are
SAMPLE
7
)