LTC1090 Linear Technology, LTC1090 Datasheet - Page 19

• Manufacturer Part Number: LTC1090
• Description: Single Chip 10-Bit Data Acquisition System
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1090 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem.
However, if large source resistances are used or if slow
settling op amps drive the inputs, care must be taken to
insure that the transients caused by the current spikes
settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1090 look like a 60pF capaci-
tor (C
Figure 9. C
“–” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog inputs
to completely settle within the allowed time.
V
V
IN
IN
+
–
IN
“ + ” INPUT
“ – ” INPUT
) in series with a 500Ω resistor (R
R
R
SOURCE
SOURCE
SCLK
ACLK
IN
CS
Figure 9. Analog Input Equivalent Circuit
gets switched between the selected “+” and
+
–
C1
C2
INPUT
INPUT
U
1
“
“
+
–
”
”
U
MUX ADDRESS
2
SHIFTED IN
4TH SCLK
LAST SCLK
3
W
R
ON
LTC1090
Figure 10. “+” and “–” Input Settling Windows
= 500Ω
SAMPLE
ON
4
) as shown in
SETTLE DURING THIS TIME
U
C
IN
“ + ” INPUT MUST
= 60pF
LTC1090 • AI16
t
SMPL
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (t
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK
cycle depending on the selected word length). The voltage
on the “+” input must settle completely within this sample
time. Minimizing R
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 4µs, R
and C1 < 20pF will provide adequate settling.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
R
“–” input source resistance must be used, the time allowed
for settling can be extended by using a slower ACLK
frequency. At the maximum ACLK rate of 2MHz, R
< 1kΩ and C2 < 20pF will provide adequate settling.
SOURCE
HOLD
“ – ” INPUT MUST SETTLE
DURING THIS TIME
1
LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)
–
1ST BIT
TEST
2
and C2 will improve settling time. If large
3
4
SOURCE
SMPL
+
, see Figure 10). The sample
and C1 will improve the input
LTC1090
LTC1090 • AI17
SOURCE
SOURCE
19
+
< 2k
1090fc
–