LTC1090 Linear Technology, LTC1090 Datasheet - Page 12

• Manufacturer Part Number: LTC1090
• Description: Single Chip 10-Bit Data Acquisition System
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1090
Unipolar Output Code (UNI = 1)
Bipolar Output Code (UNI = 0)
MSB First/LSB First Format (MSBF)
The output data of the LTC1090 is programmed for MSB
first or LSB first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1090
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB first output data, the input
word clocked to the LTC1090 should always contain a zero
in the MSBF bit location. The MSBF bit in a given D
will control the order of the next D
affects only the order of the output data word. The order
of the input word is unaffected by this bit.
Word Length (WL1, WL0)
The last two bits of the input word (WL1 and WL0) program
the output data word length of the LTC1090. Word lengths
of 8, 10, 12 or 16 bits can be selected according to the
following table. The WL1 and WL0 bits in a given D
12
OUTPUT CODE
OUTPUT CODE
1111111111
1111111110
0000000001
0000000000
0111111111
0111111110
0000000001
0000000000
1111111111
1111111110
1000000001
1000000000
•
•
•
•
•
•
•
•
•
MSBF
0
1
U
INPUT VOLTAGE
INPUT VOLTAGE
– (V
V
V
V
V
REF
REF
REF
REF
– (V
REF
–1LSB
–2LSB
1LSB
1LSB
U
0V
0V
– 1LSB
– 2LSB
– 1LSB
– 2LSB
) + 1LSB
•
•
•
•
•
•
•
•
•
REF
)
OUTPUT FORMAT
MSB First
LSB First
OUT
W
word. The MSBF bit
INPUT VOLTAGE
INPUT VOLTAGE
(V
(V
–0.0195V
–0.0098V
–4.9902V
4.9951V
4.9902V
0.0049V
4.9902V
4.9805V
0.0098V
–5.000V
REF
REF
0V
0V
•
•
•
•
•
•
•
•
•
= 5V)
= 5V)
U
IN
IN
word
word
control the length of the present, not the next, D
WL1 and WL0 are never “don’t cares” and must be set for
the correct D
word is sent. On any transfer cycle, the word length should
be made equal to the number of SCLK cycles sent by the
MPU.
Figure 2 shows how the data output (D
controlled with word length selection and MSB/LSB first
format selection.
3. Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1090 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than 1
ACLK cycle. After a change of state on the CS input, the
LTC1090 waits for two falling edges of the ACLK before
recognizing a valid chip select. One indication of CS low
recognition is the D
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
ACLK
ACLK
D
D
OUT
OUT
CS
CS
WL1
0
0
1
1
OUT
HIGH Z
word length even when a “dummy” D
WL0
OUT
0
1
0
1
LOW CS RECOGNIZED
HIGH CS RECOGNIZED
line becoming active (leaving the
INTERNALLY
INTERNALLY
OUTPUT WORD LENGTH
10 Bits
12 Bits
16 Bits
8 Bits
VALID OUTPUT
HIGH Z
OUT
) timing can be
LTC1090 • AI07
OUT
word.
1090fc
IN