AD538 Analog Devices, AD538 Datasheet - Page 7

• Manufacturer Part Number: AD538
• Description: Real-Time Analog Computational Unit ACU
• Manufacturer: Analog Devices

STABILITY PRECAUTIONS
At higher frequencies, the multistaged signal path of the AD538,
as illustrated in Figure 10, can result in large phase shifts. If a
condition of high incremental gain exists along that path (e.g.,
V
from V
Appropriate care should be exercised in board layout to pre-
vent capacitive feedback mechanisms under these conditions.
USING THE VOLTAGE REFERENCES
A stable bandgap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage out-
put of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any
voltages between +2 V and +10.2 V buffered as shown in Figure
11. The output impedance at Pin 5 is approximately 5 k . Note
that any loading of this pin will produce an error in the +10 V
reference voltage. External loads on the +2 V output should be
greater than 500 k to maintain errors less than 1%.
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pins 4 and 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
REV. C
+2V TO +10.2V
V
BUFFERED
O
V
V
11.5k
O
I
I
X
X
Z
Z
= V
50k
/ V
Figure 11. +2 V to +10.2 V Adjustable Reference
O
Y
X
to the current inputs I
LOG
LOG
REF OUT
= 1000), then small amounts of capacitive feedback
V
e
e
Z
/ V
Ln X
–
+
Ln Z
+2V
+V
–V
V
X
V
I
B
O
S
S
Z
Z
I
Figure 10. Model Circuit
= 10 V
Ln Z – Ln X
1
2
3
4
5
6
7
8
9
V
I
Y
Y
25k
0.2 M 5
OUTPUT
25k
LOG
REFERENCE
INTERNAL
VOLTAGE
10 mV/10 mV = 10 V so that
M(Ln Z – Ln X)
e
Z
+
or I
Ln Y
100
ANTILOG
+
RATIO
M(Ln Z – Ln X) +Ln Y
LOG
X
can result in instability.
ANTILOG
AD538
LOG
100
e
BUFFER
25k
V
25k
O
= V
18
17
16
15
14
13
12
11
10
Y
V
V
A
D
I
V
SIGNAL
GND
PWR
GND
C
I
V
X
Y
Z
X
X
Y
M
–7–
ONE-QUADRANT MULTIPLICATION/DIVISION
Figure 12 shows how the AD538 may be easily configured as a
precision one-quadrant multiplier/divider. The transfer function
V
a calculation not available with a conventional multiplier. In
addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range
of the AD538 greatly exceeds that of analog multipliers comput-
ing one-quadrant multiplication and division.
By simply connecting the input V
ence (Pin 4), and tying the log-ratio output at B to the antilog
input at C, the AD538 can be configured as a one-quadrant
analog multiplier with 10-volt scaling. If 2-volt scaling is desired,
V
When the input V
multiplier transfer function becomes:
As a multiplier, this circuit provides a typical bandwidth of
400 kHz with values of V
(i.e., 100 mV to 10 V). The maximum error with a 100 mV to
10 V range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 13, this error can be reduced to +0.25% of reading.
By using the +10 V reference as the V
Figure 12 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the band-
width gradually decreases to approximately 200 kHz at the
2 mV input level.
Figure 12. One-Quadrant Combination Multiplier/Divider
INPUT
OUT
X
OUTPUT
can be tied to the +2 V reference.
V
Z
+15V
–15V
= V
+10V
+2V
V
V
Y
I
B
O
Z
Z
I
(V
1
2
3
4
5
6
7
8
9
Z
25k
OUTPUT
/V
25k
X
X
REFERENCE
) allows “three” independent input variables,
INTERNAL
VOLTAGE
is tied to the +10 V reference terminal, the
V
V
V
100
O
X
O
ANTILOG
OUT
, V
RATIO
LOG
V
= V
Y
10V
Y
Y
or V
( )
AD538
LOG
X
V
V
10 V
Z
X
100
V
(Pin 15) to the +10 V refer-
Z
V
V
Z
varying over a 100:1 range
Z
X
Y
input, the circuit of
25k
25k
18
17
16
15
14
13
12
11
10
A
D
I
V
SIGNAL
GND
PWR
GND
C
I
V
X
Y
AD538
X
Y
IN4148
V
INPUT
V
INPUT
X
Y