DS42515 AMD, DS42515 Datasheet - Page 4

• Manufacturer Part Number: DS42515
• Description: MCP Flash Memory and SRAM
• Manufacturer: AMD

Key To Switching Waveforms. . . . . . . . . . . . . . . 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
4
SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . 36
Flash Read-Only Operations . . . . . . . . . . . . . . . 37
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . 38
Flash Word/Byte Configuration (CIOf) . . . . . . . . . 39
Flash Erase and Program Operations . . . . . . . . . 40
Temporary Sector/Sector Block Unprotect . . . . . . 45
Alternate CE#f Controlled Erase and Program
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Input Waveforms and Measurement
Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Timing Diagram for Alternating
Between SRAM to Flash. . . . . . . . . . . . . . . . . . 36
Figure 14. Read Operation Timings . . . . . . . . . 37
Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 38
Figure 16. CIOf Timings for Read Operations . 39
Figure 17. CIOf Timings for Write Operations. . 39
Figure 18. Program Operation Timings. . . . . . . 41
Figure 19. Accelerated Program Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 20. Chip/Sector Erase Operation
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. Back-to-back Read/Write Cycle
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22. Data# Polling Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 43
Figure 23. Toggle Bit Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44
Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 44
Figure 25. Temporary Sector/Sector Block
Unprotect Timing Diagram . . . . . . . . . . . . . . . . 45
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46
DS42515
Flash Erase And Programming Performance . . 54
Flash Latchup Characteristics. . . . . . . . . . . . . . . 54
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 54
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 54
SRAM Data Retention Characteristics . . . . . . . . 55
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57
SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 49
SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 51
FLA069—69-Ball Fine-Pitch Grid Array
8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision A (July 20, 2000) . . . . . . . . . . . . . . . . . 57
Revision B (March 7, 2001) . . . . . . . . . . . . . . . . . 57
Revision B+1 (March 15, 2001) . . . . . . . . . . . . . . 57
Figure 27. Flash Alternate CE#f Controlled Write
(Erase/Program) Operation Timings . . . . . . . . . 48
Figure 28. SRAM Read Cycle—Address
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 50
Figure 30. SRAM Write Cycle—WE# Control . . 51
Figure 31. SRAM Write Cycle—CE1#s Control. 52
Figure 32. SRAM Write Cycle—UB#s and
LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 33. CE1#s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 34. CE2s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Sector/Sector Block Protection/Unprotection . . 57
Common Flash Memory Interface (CFI) . . . . . . 57
Command Definitions . . . . . . . . . . . . . . . . . . . . 57
AC Characteristics—Alternate CE#f Controlled
Erase and Program Operations . . . . . . . . . . . . 57