D6376 NEC, D6376 Datasheet - Page 7

• Manufacturer Part Number: D6376
• Description: Search -----> UPD6376
• Manufacturer: NEC

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2.2 Supplying Clock to CLK only during Sample Data Interval
(See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.)
2.2.1 Inputting serial data (Pin 1 Low or Open)
and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B).
2.2.2 Inputting parallel data (Pin 1 High)
2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B).
Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and
D).
LRCK
CLK
The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input.
Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3)
Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure
Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in
WDCK
SI
CLK
RSI
LSI
LSB
16
A
LSB
LSB
LRCK reverse interval
16
16
A
WDCK falling
edge interval
B
MSB
1 2
B
Figure 2-4 Timing Chart of Parallel Data Input
MSB
MSB
Figure 2-3 Timing Chart of Serial Data Input
1 2
1 2
3 4
3 4
3 4
5
C
1-sample data interval
6
5
5
7
6
6
WDCK rising edge interval
8
7
7
9 10 11 12 13 14 15 16
8
8
9 10 11 12 13 14 15 16
9 10 11 12 13 14 15 16
LSB
A
D
LSB
LSB
LRCK reverse interval
A
WDCK falling
edge interval
B
MSB
1 2
PD6376
B
MSB
MSB
1 2
1 2
3 4
7
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