TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 41
TS68EN360MAB
Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
1.TS68EN360MAB.pdf
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Figure 7-26. TS68040 Internal Registers Read Cycles
Notes:
Figure 7-27. TS68040 Internal Registers Write Cycles
Notes:
2113B–HIREL–06/05
1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is
accessing an internal peripheral.
wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10
and one of the internal masters is accessing an internal peripheral.
ATTRIBUTES
(040 WRITE)
TRANSFER
(OUTPUT)
(OUTPUT)
(OUTPUT)
A31-A0
(INPUT)
(INPUT)
(INPUT)
D31-D0
(INPUT)
CLKO1
ATTRIBUTES
TBI
TA
TS
(040 WRITE)
TRANSFER
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
(INPUT)
D31-D0
A31-A0
(INPUT)
(INPUT)
MBARE
(INPUT)
CLKO1
TA
TBI
TS
C1
252
251
C1
252
C2
251
253
C2
255
253
CW
255
CW
3Ð4 CLOCKS
2Ñ4 CLOCKS
CW
CW
260
257
CW
257
254
CW
CW
254
258
C1
256
263
256
259
258
C1
TS68EN360
259
41
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