AD9520 Analog Devices, Inc., AD9520 Datasheet - Page 69

• Manufacturer Part Number: AD9520
• Description: 12 Lvpecl/24 Cmos Output Clock Generator
• Manufacturer: Analog Devices, Inc.

Table 49. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name
0F0
0F0
0F0
0F0
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
[7]
[6:5]
[4:3]
[2:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVPECL
differential
voltage
OUT0 LVPECL
power-down
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.
Selects the output type for OUT0.
Description
[7] = 0; LVPECL (default).
[7] = 1; CMOS.
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
[6:5]
00
01
10
11 (default)
Sets the output polarity for OUT0.
[7]
0 (default)
0
1
1
1
1
Sets the LVPECL output differential voltage (V
[2]
0
0
1 (default)
1
LVPECL power-down.
[0] = 0; normal operation (default).
[0] = 1; safe power-down.
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
[7]
0
1
1
OUT0A
Tristate
On
Tristate
On
[4]
X
X
0 (default)
0
1
1
[1]
0
1
0 (default)
1
CSDLD Signal OUT7 Enable Status
0
0
1
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OUT0B
Tristate
Tristate
On
On
[3]
0 (default)
1
0
1
0
1
V
400
600
780
960
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enable OUT7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect
and set the enable LD pin comparator bit (0x01D[3]).
OD
(mV)
OD
).
Output Type
LVPECL
LVPECL
CMOS
CMOS
CMOS
CMOS
OUT0A
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Inverting
Noninverting
Noninverting
Inverting
Noninverting
OUT0B
Inverting
AD9520-5