AD9049 Analog Devices, Inc., AD9049 Datasheet - Page 9

• Manufacturer Part Number: AD9049
• Description: 9-bit, 30 Msps Adc
• Manufacturer: Analog Devices, Inc.

REV. A
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9049 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +2.788 V to
3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and shut the T/H off. The digital outputs are locked at their
maximum or minimum value (i.e., all “0” or all “1”). This pre-
cludes the digital outputs from changing to an invalid value
when the analog input is out of range.
When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T/H back to the active
mode and the device recovers in approximately 10 ns.
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to –1.0 V.
Timing
The performance of the AD9049 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as 10%
will cause no degradation in performance (see Figure 13, SNR
vs. Clock Pulse Width).
The AD9049 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t
after the rising edge of the encode command (refer to the
AD9049 Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce tran-
sients within the AD9049; these transients can detract from the
converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9049 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T/H
switches to a track function only. This precludes the T/H from
drooping to the rail during the conversion process and mini-
mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. The AD9049 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. This requires 5 clock pulses each time the
clock is restarted for the first valid data output (refer to Fig-
ure 2 Timing Diagram).
PD
)
–9–
Power Dissipation
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 30 MSPS,
analog input is –1 dBFS at 10.3 MHz, the digital outputs are
loaded with approximately 7 pF (10 pF maximum), and V
5 V. These conditions intend to reflect actual usage of the device.
As shown in Figure 4, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to USING THE AD9049,
3 V System). The lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9049 (Pin 3, V
reference is used by strapping Pins 3 and 4 of the AD9049 to-
gether. The internal reference has 500 A of extra drive current
that can be used for other circuits.
Some applications may require greater accuracy, improved tem-
perature performance or adjustment of the gain of the AD9049,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9049. The VREF
drive current.
The input range can be adjusted by varying the reference volt-
age applied to the AD9049. No appreciable degradation in per-
formance occurs when the reference is adjusted 5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
REF
Output). In normal operation the internal
IN
requires 5 A of
AD9049
DD
is