CY7C4285V-15ASI Cypress Semiconductor Corp, CY7C4285V-15ASI Datasheet - Page 18
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CY7C4285V-15ASI
Manufacturer Part Number
CY7C4285V-15ASI
Description
IC FIFO 64KX18 SYNCHRONOUS 64QFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C4255V-15ASXC.pdf
(24 pages)
Specifications of CY7C4285V-15ASI
Function
Synchronous
Memory Size
1.1K (64 x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4285V-15ASI
Manufacturer:
CYPRESS
Quantity:
1 650
Company:
Part Number:
CY7C4285V-15ASI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document Number: 38-06012 Rev. *D
32. If a write is performed on this rising edge of the write clock, there are Full (m1) words of the FIFO when PAF goes LOW.
33. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V.
34. t
and the rising edge of WCLK is less than t
SKEW3
D
WCLK
WCLK
RCLK
0
WEN
WEN
REN
PAF
–D
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
LD
17
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
t
CLKH
t
CLKH
FULL – M + 1 WORDS
(continued)
t
CLK
t
t
ENS
ENS
SKEW3
t
IN FIFO
DS
t
PAE OFFSET
ENS
, then PAF may not change state until the next WCLK rising edge.
Figure 17. Write Programmable Registers
t
ENH
t
CLKL
t
CLKL
t
ENH
t
DH
Note
32
PAF OFFSET
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
t
[34]
ENS
PAE OFFSET
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
D
0
[33]
– D
t
ENH
11
t
PAF synch
Page 18 of 24
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