ST62T35B ST Microelectronics, ST62T35B Datasheet - Page 28

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ST62T35B

Manufacturer Part Number
ST62T35B
Description
(ST62E35B / ST62T35B) 8-BIT OTP/EPROM MCUs
Manufacturer
ST Microelectronics
Datasheet
27
ST62T35B/E35B
IINTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh — Read/Write
In conjunction with IOR register ESB bit, the polar-
ity of I/O pins triggered interrupts can be selected
by setting accordingly the Interrupt Polarity Regis-
ter (IPR). If a bit in IPR is set to one the corre-
sponding port interrupt is inverted (e.g. IPR bit 2 =
1 ; port C generates interrupt on rising edge. At re-
Tables 11. I/O Interrupts selections according to IPR, IOR programming
28/82
7
-
GEN
GEN
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
-
IPR3
IPR4
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IPR2
-
0
1
PortE PortD PortC PortA PortB
IPR0
IPR1
0
0
1
1
0
0
1
1
X
0
0
1
1
0
0
1
1
X
IOR5
IOR6
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port C occurence
0
falling edge
rising edge
Port B occurence
Port A occurence
falling edge
falling edge
falling edge
falling edge
falling edge
falling edge
rising edge
rising edge
rising edge
rising edge
rising edge
rising edge
high level
high level
Disabled
Disabled
low level
low level
set, IPR is cleared and all port interrupts are not
inverted (e.g. Port C generates interrupts on fall-
ing edges).
Bit 7 - Bits 5 = Unused .
Bit 4 = Port E Interrupt Polarity .
Bit 3 = Port D Interrupt Polarity .
Bit 2 = Port C Interrupt Polarity .
Bit 1= Port A Interrupt Polarity .
Bit 0 = Port B Interrupt Polarity .
Port D occurence
Port E occurence
falling edge
falling edge
falling edge
falling edge
falling edge
falling edge
rising edge
rising edge
rising edge
rising edge
rising edge
rising edge
high level
high level
Disabled
Disabled
low level
low level
Interrupt source
0
Interrupt
Interrupt
source
source
2
1

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