CY7C4231V-15JXCT Cypress Semiconductor Corp, CY7C4231V-15JXCT Datasheet - Page 9
![IC SYNC FIFO MEM 2KX9 32-PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7C4231V-15JXCT
Manufacturer Part Number
CY7C4231V-15JXCT
Description
IC SYNC FIFO MEM 2KX9 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C4241V-15AXC.pdf
(18 pages)
Specifications of CY7C4231V-15JXCT
Function
Synchronous
Memory Size
18K (2K x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4231V-15JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06010 Rev. *B
Switching Waveforms
Write Cycle Timing
Read Cycle Timing
Notes:
12. t
11. t
REN1,REN2
(if applicable)
REN1,REN2
between the rising edge of RCLK and the rising edge of WCLK is less than t
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
0
RCLK
RCLK
0
–D
–Q
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
OE
FF
EF
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
[11]
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CKL
t
SKEW1
NO OPERATION
[12]
t
DS
t
t
CLKL
CLKL
t
ENS
SKEW1
SKEW1
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
CY7C4421V/4201V/4211V/4221V
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
CY7C4231V/4241V/4251V
t
OHZ
NO OPERATION
NO OPERATION
Page 9 of 18