CY7C4261-15JXC Cypress Semiconductor Corp, CY7C4261-15JXC Datasheet - Page 12

• Manufacturer Part Number: CY7C4261-15JXC
• Description: IC DEEP SYNC FIFO 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-15JXC

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06015 Rev. *D
21. t
22. PAE offset= n.
23. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW
24. If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271.
27. t
and the rising RCLK is less than t
RCLK and the rising edge of WCLK is less than t
(if applicable)
SKEW2
SKEW2
(if applicable)
WEN2
WCLK
REN1,
WEN1
RCLK
REN2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of
WEN2
PAE
WCLK
WEN1
REN1,
RCLK
REN2
PAF
t
CLKH
t
CLKH
SKEW2
(continued)
FULL − (M + 1) WORDS
, then PAE may not change state until the next RCLK.
t
ESKEW2
Figure 12. Programmable Almost Empty Flag Timing
Figure 13. Programmable Almost Full Flag Timing
IN FIFO
SKEW2
t
t
ENS
ENS
[21]
t
t
ENS
ENS
, then PAF may not change state until the next WCLK.
t
t
ENH
ENH
t
t
ENH
ENH
t
CLKL
t
CLKL
t
PAE
22
Note
24
25
t
PAF
t
ENS
t
ENS
t
SKEW2
FULL − M WORDS
N + 1 WORDS
IN FIFO
t
ENS
IN FIFO
[27]
t
ENS
[26]
t
ENH
CY7C4261, CY7C4261
t
ENH
t
PAF
23
Page 12 of 19
t
PAE
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