CY7C4231V-15JXC Cypress Semiconductor Corp, CY7C4231V-15JXC Datasheet - Page 10
![IC SYNC FIFO MEM 2KX9 LV 32-PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7C4231V-15JXC
Manufacturer Part Number
CY7C4231V-15JXC
Description
IC SYNC FIFO MEM 2KX9 LV 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C4241V-15AXC.pdf
(18 pages)
Specifications of CY7C4231V-15JXC
Function
Synchronous
Memory Size
18K (2K x 9)
Data Rate
66MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
18Kb
Access Time (max)
11ns
Word Size
9b
Organization
2Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
20mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1759-5
CY7C4231V-15JXC
CY7C4231V-15JXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4231V-15JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C4231V-15JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06010 Rev. *B
Switching Waveforms
Reset Timing
Notes:
13. The clocks (RCLK, WCLK) can be free-running during reset.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
WEN2/LD
for the programmable flag offset registers.
Q
EF,PAE
FF,PAF,
REN1,
WEN1
0 −
REN2
RS
[15]
Q
8
[13]
(continued)
t
t
t
RSF
RSF
RSF
t
RS
t
t
t
RSS
RSS
RSS
CY7C4421V/4201V/4211V/4221V
t
t
t
RSR
RSR
RSR
CY7C4231V/4241V/4251V
OE=0
O
E
=1
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