CY7C4211-15AC Cypress Semiconductor Corp, CY7C4211-15AC Datasheet - Page 9

IC SYNC FIFO MEM 512X9 32-TQFP

CY7C4211-15AC

Manufacturer Part Number
CY7C4211-15AC
Description
IC SYNC FIFO MEM 512X9 32-TQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheets

Specifications of CY7C4211-15AC

Function
Synchronous
Memory Size
4.6K (512 x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP
Configuration
Dual
Density
4Kb
Access Time (max)
10ns
Word Size
9b
Organization
512x9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1211

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4211-15AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06016 Rev. *B
Switching Waveforms
Read Cycle Timing
Reset Timing
Notes:
WEN2/LD
15. t
16. t
REN1,REN2
between the rising edge of RCLK and the rising edge of WCLK is less than t
between the rising edge of WCLK and the rising edge of RCLK is less than t
Q
SKEW1
SKEW1
Q
EF,PAE
FF,PAF,
WEN1
WEN2
WCLK
RCLK
0
REN1,
WEN1
0 -
REN2
–Q
OE
EF
RS
[18]
Q
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
8
8
[17]
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
t
t
t
t
RSS
RSS
RSS
CKL
t
SKEW1
NO OPERATION
[16]
t
CLKL
SKEW1
SKEW1
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
VALID DATA
t
t
t
RSR
RSR
RSR
t
REF
CY7C4421/4201/4211/4221
t
OHZ
CY7C4231/4241/4251
OE=0
OE=1
Page 9 of 18
[19]

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