CY7C4211-15AC Cypress Semiconductor Corp, CY7C4211-15AC Datasheet - Page 4

• Manufacturer Part Number: CY7C4211-15AC
• Description: IC SYNC FIFO MEM 512X9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4211-15AC

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 4Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 512x9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1211

Document #: 38-06016 Rev. *B
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the Read
and Write pointers.
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421. (64 – m), CY7C4201
Table 2. Status Flags
0
1 to n
(n + 1) to 32
33 to (64 – (m + 1))
(64 – m)
64
0
1 to n
(n + 1) to 512
513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
(1024 – m)
1024
Notes:
1.
2.
3.
The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of
RCLK.
n = Empty Offset (n = 7 default value).
m = Full Offset (m = 7 default value).
[2]
[2]
CY7C4221
CY7C4421
[3]
to 63
[3]
to 1023
0
1 to n
(n + 1) to 1024
(2048 – m)
2048
0
1 to n
(n + 1) to 128
129 to (256 – (m + 1))
(256 – m)
256
[2]
CY7C4231
Number of Words in FIFO
[2]
[3]
Number of Words in FIFO
to 2047
[3]
CY7C4201
to 255
0
1 to n
(n + 1) to 2048
(4096 – m)
4096
[2]
CY7C4241
[3]
0
1 to n
(n + 1) to 256
257 to (512 – (m + 1))
(512 – m)
512
to 4095
(256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m),
CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251
(8K – m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 1. Writing the Offset Registers
LD
0
0
1
1
[2]
[3]
WEN
CY7C4211
0
1
0
1
to 511
0
1 to n
(n + 1) to 4096
(8192 – m)
8192
[2]
WCLK
CY7C4251
CY7C4421/4201/4211/4221
[3]
[1]
to 8191
CY7C4231/4241/4251
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
FF
H
H
H
H
H
L
FF
H
H
H
H
H
L
Selection
PAF
H
H
H
H
L
L
PAF
H
H
H
H
L
L
PAE
Page 4 of 18
H
H
H
H
L
L
PAE
H
H
H
H
L
L
EF
H
H
H
H
H
EF
L
H
H
H
H
H
L