CS8416-IS Cirrus Logic, CS8416-IS Datasheet - Page 39

• Manufacturer Part Number: CS8416-IS
• Description: 192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: Cirrus Logic

DS578PP2
AUDIO
96KHZ
RCBL
U
C
TX
SDOUT
OLRCK
OSCLK
OMCK
RMCK
15
16
17
18
19
20
26
28
27
25
24
Audio Channel Status Bit(output) – When low, a valid linear PCM audio stream is indicated.
96 khz Sample Rate Detect(output)
the sample rate is ≥ 88.1 KHz. Otherwise output indeterminate.
Receiver Channel Status Block
block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames
and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK.
User Data ( Output ) - Outputs user data from the AES3 receiver, clocked by the rising and falling
edges of OLRCK.
Channel Status Data ( Output ) - Outputs channel status data from the AES3 receiver, clocked by the
ris ing and falling edges of OLRCK.
S/PDIF MUX Pass through ( Output)
Serial Audio Output Data ( Output ) - Audio data serial output pin. This pin must be pulled to low to
DGND through a 47 K Ω resistor.
Serial Audio Output Left/Right Clock ( Input / Output ) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs).
Serial Audio Output Bit Clock ( Input / Output ) - Serial bit clock for audio data on the SDOUT pin.
System Clock ( Input ) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as
reference signal for OMCK/RMCK ratio expressed in register 24
Recovered Master Clock ( Output ) - Recovered master clock output when PLL is locked to the
incoming AES3 stream. Frequency is 128/256x the sample rate (Fs).
(
Output
-
if input sample rate is ≤ 48 KHz, ouputs a “0”. Outputs a “1” if
) -
Indicates the beginning of a received channel status
CS8416
39