CS8415A Cirrus Logic, CS8415A Datasheet - Page 20
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CS8415A
Manufacturer Part Number
CS8415A
Description
96 kHz DIGITAL AUDIO INTERFACE RECEIVER
Manufacturer
Cirrus Logic
Datasheet
1.CS8415A.pdf
(42 pages)
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1
2
4
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14-1D
1E
1F-37
7F
7. CONTROL PORT REGISTER SUMMARY
Addr(Hex)
7.1
Note:
20
INCR
7
Memory Address Pointer (MAP)
INCR - Auto Increment Address Control Bit
MAP6:MAP0 - Register address
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8415A.
Control 1
Control 2
Clock Source Control
Serial Output Format
Interrupt 1 Status
Interrupt 2 Status
Interrupt 1 Mask
Interrupt 1 Mode (MSB)
Interrupt 1 Mode (LSB)
Interrupt 2 Mask
Interrupt 2 Mode (MSB)
Interrupt 2 Mode (LSB)
Receiver CS Data
Receiver Errors
Receiver Error Mask
CS Data Buffer Control
U Data Buffer Control
Q sub-code Data
OMCK/RMCK Ratio
C or U Data Buffer
ID and Version
Default = ‘0’
0 - Disabled
1 - Enabled
Function
MAP6
6
MAP5
5
SWCLK
SOMS
ORR7
AUX3
Table 2. Control Register Map Summary
ID3
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSLIPM
QCRCM
OSLIP1
OSLIP0
HOLD1
OSLIP
QCRC
SOSF
ORR6
AUX2
RUN
ID2
MAP4
6
0
0
0
0
0
0
0
4
MUTESAO
SORES1
CCRCM
HOLD0
CCRC
ORR5
AUX1
BSEL
ID1
5
0
0
0
0
0
0
0
0
0
0
MAP3
3
UNLOCKM
UNLOCK
SORES0
RMCKF
CBMR
ORR4
AUX0
ID0
4
0
0
0
0
0
0
0
0
0
0
0
MAP2
SOJUST
DETUM
DETU1
DETU0
DETCI
ORR3
DETU
VER3
MMR
2
PRO
VM
3
0
0
0
0
0
0
V
0
CONFM
DETCM
SODEL
DETC1
DETC0
AUDIO
CONF
MUX2
DETC
ORR2
VER2
INT1
2
0
0
0
0
0
0
0
MAP1
1
SOSPOL
QCHM
DETUI
MUX1
QCH1
COPY
ORR1
QCH0
VER1
BIPM
QCH
CAM
INT0
BIP
CS8415A
1
0
0
0
0
0
DS470PP3
MAP0
SOLRPOL
RERRM
RERR1
RERR0
0
MUX0
RERR
PARM
ORR0
ORIG
VER0
CHS
PAR
0
0
1
0
0
0
0
0