CS4361 Cirrus Logic, CS4361 Datasheet - Page 13

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CS4361

Manufacturer Part Number
CS4361
Description
6-channel D/A Converter
Manufacturer
Cirrus Logic
Datasheet

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DS672A2
S D A T A
S D A T A
I
MCLK/LRCK = 1024, 512, 256, 128, or 64
I
MCLK/LRCK = 768, 384, 192, or 96
I
MCLK/LRCK = 1152
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
2
2
2
LR C K
LR C K
S C L K
S C L K
S, 16-Bit data and INT SCLK = 32 Fs if
S, Up to 24-Bit data and INT SCLK = 48 Fs if
S, Up to 24-Bit data and INT SCLK = 72 Fs if
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK.
The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode
is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the
digital de-emphasis function. Refer to Figures 7 - 12 for details.
MSB -1 -2 -3 -4 -5
M SB -1 -2 -3 -4 -5
Internal SCLK Mode
Internal SCLK Mode
Le ft C ha n nel
+5 +4
Le ft C ha n nel
+5 +4
Figure 8. CS4361 Data Format (Left Justified)
+3 +2 +1 LSB
+3 +2 +1 LS B
Figure 7. CS4361 Data Format (I
I
Data Valid on Rising Edge of SCLK
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
2
S, up to 24-Bit Data
M SB -1 -2 -3 -4
MSB -1 -2 -3 -4
External SCLK Mode
External SCLK Mode
2
S)
+5 +4
+5 +4
R ig h t C ha n nel
R ig h t C ha n nel
+3 +2 +1 LSB
+3 +2 +1 LS B
CS4361
13

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