MD4811-d512-MECH-P M-Systems, MD4811-d512-MECH-P Datasheet - Page 79

• Manufacturer Part Number: MD4811-d512-MECH-P
• Description: DiskOnChip-Based MCP Including Mobile DiskOnChip G3 and Mobile RAM
• Manufacturer: M-Systems

62
Read/Write
Description
Reset Value
Bit No.
15-10
9-0
NEGATE_COUNT. When the EDGE bit of the DMA Control register[0] is 0, this bit must be
Reserved for future use.
programmed to specify the bus cycle in which DMARQ# will be negated, as follows:
NEGATE_COUNT = BYTES_REMAINING + 16 + BYTES_PER_CYCLE.
Example: To negate DMARQ# at the beginning of the cycle in which the last word is to be
transferred by a 16-bit host: NEGATE_COUNT = 2 + 16 + 2 = 20.
0
0
Bits 15-10
RFU_0
R
DMA Control Register [1]
Data Sheet, Rev. 1.1
0
Description
0
0
NEGATE_COUNT
0
Bits 9-0
R/W
Mobile DiskOnChip G3
0
91-SR-011-05-8L
0