ST8016T Sitronix Technology, ST8016T Datasheet - Page 7

• Manufacturer Part Number: ST8016T
• Description: COM/SEG LCD Driver
• Manufacturer: Sitronix Technology

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7
7.1
(Segment mode)
Preliminary Ver 0.12
/DISPOFF
ElO
SYMBOL
V
V
V
DI
LGND
12L
43L
GND
XCK
0L
S/C
V
L/R
MD
V
FR
1
7
LP
, V
, V
, V
, EIO
-DI
DD
SS
FUNCTIONAL
Pin Functions
0R
12R
43R
0
2
Logic system power supply pin
Ÿ Connected to +2.5 to +5.5 V.
Ground pin
Logic system power ground pin
Ÿ Do not short LGND with GND and Vss by ITO on LCD panel
Ÿ Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Ÿ Normally use the bias voltages set by a resistor divider
Ÿ Ensure that voltages are set such that V
Ÿ V
Input pins for display data
Clock input pin for taking display data
Latch pulse input pin for display data
Input pin for selecting the reading direction of display data
Control input pin for output of non-select level
AC signal input pin for LCD drive waveform
Mode selection pin
Segment mode/common mode selection pin
Input/output pins for chip selection
Ÿ In 4-bit parallel mode, DI
Ÿ In 8-bit parallel mode, All DI
Ÿ Refer to section 7.2.2.
Ÿ Data is read at the falling edge of the clock pulse.
Ÿ Data is latched at the falling edge of the clock pulse.
Ÿ When set to LGND level "L", data is read sequentially from Y
Ÿ When set to V
Ÿ Refer to section 7.2.2.
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
Ÿ When set to LGND level "L", the LCD drive output pins (Y
Ÿ When set to "L", the contents of the line latch are reset, but the display data are read in the
Ÿ Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
Ÿ Normally it inputs a frame inversion signal.
Ÿ The LCD drive output pins' output voltage levels can be set using the line latch output signal
Ÿ Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Ÿ When set to LGND level "L", 4-bit parallel input mode is set.
Ÿ When set to V
Ÿ Refer to section 7.2.2.
Ÿ When set to V
Ÿ When L/R input is at LGND level "L", ElO
Ÿ When L/R input is at V
Ÿ During output, set to "H" while LP • XCK is "H" and after 160 bits of data have been read, set
Ÿ During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is
voltage which is assigned by specification for each power pin
to LGND or V
controls the LCD drive circuit.
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled
the driver outputs non-select level (V
the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to
what is shown in AC characteristics, it cannot output the reading data correctly.
controls the LCD drive circuit.
and the FR signal.
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H".
iL
and V
iR
DESCRIPTION
(i = 0,12, 43) must connect to an external power supply, and supply regular
DD
DD
DD
DD
.
level "H", data is read sequentially from Y
level "H", 8-bit parallel input mode is set.
level "H", segment mode is set.
DD
3
level "H", ElO
-DI
7
0
-Dl
Page 7/27
are the display data input pins, and DI
0
pins are the display data input pins.
12
1
or V
FUNCTION
is set for input, and EIO
SS
1
< V
is set for output, and EIO
43
), then outputs the contents of the data latch at
43
< V
12
< V
0
1
.
1
-Y
to Y
160
160
) are set to level Vss.
to Y
160
2
is set for output.
.
1
2
7
.
is set for input.
-DI
4
must be connected
2007/10/29
ST8016T