MT8980DE1 Zarlink Semiconductor, Inc., MT8980DE1 Datasheet - Page 5

• Manufacturer Part Number: MT8980DE1
• Description: 256 x 256 Channels (8 TDM Streams at 2.048 Mbps) Non-blocking Digital Switch (DX)
• Manufacturer: Zarlink Semiconductor, Inc.

The higher order bits come from the Control
Register, which may be written to or read from via
the Control Interface. The lower order bits come
from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory
and writes are to the Connection Memory Low. The
Connection
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT8980s to be constructed.
CSTo pin.
All
signals C4i and F0i.
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.
BIT
4-3
2-0
7
6
5
ST-BUS
Select Bits
Message
(unused)
Address
Memory
Memory
Stream
NAME
Mode
Split
Bits
Memory
timing is
When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
The number expressed in binary notation on these bits refers to the input or output ST-BUS
stream which corresponds to the subsection of memory made accessible for subsequent
operations.
High
derived from the two
7
determines
Control
Mode
It also controls the
Bits
6
Figure 4 - Control Register Bits
(unused)
5
whether
4
Memory
Select
Bits
3
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection
regardless of the actual values.
DESCRIPTION
2
Address
Stream
Bits
1
Memory
0
High
location
MT8980D
were
2-7
1,