MT8962AS Zarlink Semiconductor, Inc., MT8962AS Datasheet
MT8962AS
Available stocks
Related parts for MT8962AS
MT8962AS Summary of contents
Page 1
Features ST-BUS compatible • • Transmit/Receive filters & PCM Codec in one I.C • Meets AT&T D3/D4 and CCITT G711 and G712 µ -Law: MT8960/62/64/67 • • A-Law: MT8961/63/65/67 • Low power consumption: Op typ. Stby.: 2.5 ...
Page 2
MT8960/61/62/63/64/65/66/67 MT8960/61/64/65 1 CSTi 2 DSTi C2i 3 DSTo 4 5 VDD F1i SD3 8 SD2 9 18 PIN CERDIP/PDIP Pin Description Pin Name CSTi Control ST-BUS TTL-compatible digital input used to control the ...
Page 3
MT8960/61/62/63/64/65/66/67 ISO -CMOS MT8960/62 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 -2.415V -1.207V 0V +1.207V +2.415V Bit 7... 0 Analog Input Voltage (V MSB LSB Figure ...
Page 4
MT8960/61/62/63/64/65/66/67 Functional Description Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code ...
Page 5
V Ref An external voltage must be supplied to the V which provides the reference voltage for the digital encoding and decoding of the analog signal. For V = 2.5V, the digital encode decision value for Ref overload (maximum analog ...
Page 6
MT8960/61/62/63/64/65/66/67 Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input ...
Page 7
Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data is being input and output, and the control word at CSTi enters Register A. ...
Page 8
MT8960/61/62/63/64/65/66/67 Logic Control Outputs SD0-5 These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B causes the SD outputs to assume an inactive state. A logic high (V ...
Page 9
Powerdown Powerdown of the chip is achieved in several ways: Internal Control: 1) Initial Power-up. Initial application causes powerdown for a period of 25 clock EE cycles and during this period the chip will accept input only ...
Page 10
MT8960/61/62/63/64/65/66/67 Speech Switch - 8980 Controlling Micro- Processor Control & Signalling - 8980 Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67 6-28 2 ISO -CMOS DSTi V X DSTo V R CDTi SD0 . ...
Page 11
Absolute Maximum Ratings* Parameter 1 DC Supply Voltages 2 Reference Voltage 3 Analog Input 4 Digital Inputs 5 Output Voltage 6 Current On Any Pin 7 Storage Temperature 8 Power Dissipation at 25°C (Derate 16 mW/ * Exceeding these values ...
Page 12
MT8960/61/62/63/64/65/66/67 DC Electrical Characteristics (cont’d) Characteristics 6 Output Low DSTo D Voltage Output High DSTo I Voltage Output Resistance Output Capacitance DSTo 10 Input Current Input ...
Page 13
AC Electrical Characteristics (cont’d) Characteristics 17 Propagation Delay D Clock to SD Output Output Fall Time Output Rise Time Digital Loopback L Time DSTi to DSTo (See Figures 9a, 9b, ...
Page 14
MT8960/61/62/63/64/65/66/67 Transmit (A/D) Path (cont’d) Characteristics Quantization CCITT G712 Distortion (Method 2) (cont’d) AT&T (See Figure 13) 7 Idle Channel C-message Noise Psophometric 8 Single Frequency Noise 9 Harmonic Distortion (2nd or 3rd Harmonic) 10 Envelope Delay 11 Envelope Delay ...
Page 15
AC Electrical Characteristics - Receive (D/A) Path ° ± ± =5V 5%, V =-5V 5 Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics 1 Analog output at ...
Page 16
MT8960/61/62/63/64/65/66/67 Receive (D/A) Path (cont’d) Characteristics 11 Envelope Delay 12 Envelope Delay 1000-2600 Hz Variation with 600-3000 Hz Frequency 400-3200 Hz <200 Hz 13 Gain Relative to Gain @ 1004 Hz 200 Hz A (See Figure 11) 300-3000 Hz N ...
Page 17
C2i 50% Input 10 90% F1i Input 10 DSTo high Output impedance t PZL t PZH Figure 9b - Timing Diagram - Output Enable Note: In typical applications, F1i will remain ...
Page 18
MT8960/61/62/63/64/65/66/67 SCALE B SCALE A PASSBAND ATTENUATION 0 -0.125 0. Attenuation Relative To Attenuation At 1 kHz (dB 5060 100 200 Figure 10 - Attenuation vs Frequency for Transmit (A/D) ...
Page 19
ISO 5a. CCITT Method 1 CCITT End-To-End Spec +1.0 +0.5 +0.25 0 -60 -55 -50 -40 -0.25 -0.5 -1.0 Bandlimited White Noise Test Signal 5b. CCITT Method 2 +1.5 +1.0 +0.5 +0.25 0 -60 -50 -0.25 -0.5 -1.0 -1.5 Sinusoidal ...
Page 20
MT8960/61/62/63/64/65/66/67 6a. CCITT Method 29.3 20 14.3 12 -60 -55 -50 6b. CCITT Method 25.4 24 -60 -50 Figure 13 - Signal to Total Distortion Ratio vs Input Level ...
Page 21
ISO 1000 750 500 370 (600Hz) 250 125 0 500 Figure 14 - Envelope Delay Variation Frequency 5 4 *Relative to Fundamental Output power level with +3dBm0 input signal level at a frequency of 1.02kHz. Figure ...
Page 22
MT8960/61/62/63/64/65/66/67 Notes: 6-40 2 ISO -CMOS ...
Page 23
Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
Page 24
Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
Page 25
16-Pin DIM Min Max Min A 0.093 0.104 0.093 (2.35) (2.65) (2.35) A 0.004 0.012 0.004 1 (0.10) (0.30) (0.10) B 0.013 0.020 0.013 (0.33) (0.51) (0.33) C 0.009 0.013 0.009 (0.231) (0.318) (0.231) D 0.398 0.413 ...
Page 26
For more information about all Zarlink products visit our Web Site at www.zarlink.com ’ ’ “ ” ...