MT8888CN Zarlink Semiconductor, Inc., MT8888CN Datasheet - Page 2

• Manufacturer Part Number: MT8888CN
• Description: Integrated DTMF Transceiver with Intel Micro Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MT8888C
Pin Description
2
14-
20
10
11
12
13
17
18
19
20
1
2
3
4
5
6
7
8
9
Pin #
18-21 D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
16,17
8, 9,
24
10
11
12
13
14
15
22
23
24
1
2
3
4
5
6
7
Name
OSC1 DTMF clock/oscillator input. Connect a 4.7M resistor to VSS if crystal oscillator is used.
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
TONE Output from internal DTMF transmitter.
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
RS0
V
V
V
WR
IRQ/
ESt
GS
RD
NC
IN+
IN-
CS
CP
TONE
OSC1
OSC2
Ref
DD
SS
VRef
VSS
WR
IN+
GS
CS
IN-
20 PIN PLASTIC DIP/SOIC
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage output (V
Ground (0V).
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
Write microprocessor input. TTL compatible.
Chip Select input. Active Low. This signal must be qualified externally by address latch
enable (ALE) signal, see Figure 12.
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
Read microprocessor input. TTL compatible.
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
TTL compatible.
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (5V typical).
No Connection.
10
1
2
3
4
5
6
7
8
9
TSt
20
19
18
17
16
15
14
13
12
11
frees the device to accept a new tone pair. The GT output acts to reset the
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
Figure 2 - Pin Connections
DD
/2).
Description
OSC1
OSC2
TONE
VRef
VSS
WR
IN+
NC
NC
GS
CS
IN-
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
RD
RS0
TSt
detected at St