MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 9

• Manufacturer Part Number: MT9171AE
• Description: Interface, Digital Subscriber Interface Circuit
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
the C-channel and D-Channel also at
kbit/s.
In DN mode, both the DV and CD ports operate as
ST-BUS streams at 2.048 Mbit/s.
transfers data over pins DSTi and DSTo while on the
CD port, the CDSTi and CDSTo pins are used. The
SINGL port option only exists in DN mode.
In MOD mode, DUAL port operation must be used
and the D, B1 and B2 channel designations no
longer exist. The selection of SLV or MAS will
determine which of the DNICs is using the externally
supplied clock and which is phase locking to the data
SINGL
Mode
DUAL
Mode
MAS
MOD
ODE
SLV
D-C
C-D
DN
#
0
1
2
3
4
5
6
7
SLAVE
crystal is phase locked to it to provide clocks for the entire device and are output for the external
system to synchronize to.
MASTER
which must be frequency locked. The transmit data is synchronized to the system timing with the
receive data recovered by a clock extracted from the receive data and resynchronized to the system
timing.
DUAL PORT
and the DV port transferring the B1& B2 channels.
SINGLE PORT - The B1& B2, C and D channels are all transferred through the DV port. The CD
port is disabled and CDSTi should be pulled high.
MODEM
through the DV port at the baud rate selected. The C-channel is transferred through the CD port
also at the baud rate and is synchronized to the CLD output.
DIGITAL NETWORK
2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN
recommendation.
D BEFORE C-CHANNEL
C BEFORE D-CHANNEL
OUTPUT DATA ENABLE
impedance state. This is intended for power-up reset to avoid bus contention and possible damage
to the device during the initial random state in a daisy chain configuration of DNICs. In all the other
modes of operation DV and CD ports are enabled during the appropriate channel times.
Name
CLD
CLD
F0
F0
F0
F0
F0
F0
-
-
The chip timebase is extracted from the received line data and the external 10.24 MHz
-
Baseband operation at 80 or 160 kbits/s. The line data is received and transmitted
The timebase is derived from the externally supplied data clocks and 10.24 MHz clock
F0/CLD
-
Both the CD and DV ports are active with the CD port transferring the C&D channels
Input/Output
Output
Output
Output
Output
-
Input
Input
Input
Input
Intended for use in the digital network with the DV and CD ports operating at
The DV port
-
-
-
When mode 7 is selected, the DV and CD ports are put in high
The D-channel is transferred before the C-channel following F0.
The C-channel is transferred before the D-channel following F0.
80 or 160
Table 3. Pin Configurations
Table 2. Mode Definitions
Name
RCK
RCK
F0o
F0o
F0o
F0o
F0o
F0o
Function
F0o/RCK
on the line. Due to jitter and end to end delay, one
end must be the master to generate all the timing for
the link and the other must extract the timing from
the receive data and synchronize itself to this timing
in order to recover the synchronous data. DUAL port
mode allows the user to use two separate serial
busses: the DV port for PCM/data (B channels) and
the CD port for control and signalling information (C
and D channels). In the SINGL port mode, all four
channels are concatenated into one serial stream
and input to the DNIC via the DV port. The order of
the C and D channels may be changed only in DN/
DUAL mode. The DNIC may be configured to transfer
the D-channel in channel 0 and the C-channel in
Input/Output
Output
Output
Output
Output
Output
Output
Output
Output
Name
TCK
TCK
C4
C4
C4
C4
C4
C4
C4/TCK
MT9171/72
Input/Output
Output
Output
Output
Output
Input
Input
Input
Input
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