CY7C4275-15ASC Cypress Semiconductor Corp, CY7C4275-15ASC Datasheet - Page 7
![IC DEEP SYN FIFO 32KX18 64-STQFP](/photos/6/76/67621/428-64-tqfp_sml.jpg)
CY7C4275-15ASC
Manufacturer Part Number
CY7C4275-15ASC
Description
IC DEEP SYN FIFO 32KX18 64-STQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C4275-15ASC.pdf
(20 pages)
Specifications of CY7C4275-15ASC
Function
Synchronous
Memory Size
576K (32K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Configuration
Dual
Density
576Kb
Access Time (max)
10ns
Word Size
18b
Organization
32Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
50mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4275-15ASC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06008 Rev. *B
Read Cycle Timing
Write Cycle Timing
Notes:
14. t
15. t
Q
D
rising edge of RCLK and the rising edge of WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
0
0
SKEW1
SKEW2
WCLK
WCLK
RCLK
RCLK
WEN
–Q
WEN
–D
REN
REN
OE
FF
EF
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
[14]
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CLK
SKEW1
SKEW2
t
SKEW2
NO OPERATION
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
[15]
t
DS
t
t
CLKL
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
CY7C4275
CY7C4285
Page 7 of 20
4275–6
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