CY7C4275-15ASC Cypress Semiconductor Corp, CY7C4275-15ASC Datasheet
CY7C4275-15ASC
Specifications of CY7C4275-15ASC
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CY7C4275-15ASC Summary of contents
Page 1
... FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4275/85 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... Functional Description (continued) The CY7C4275/85 provides five status pins. These pins are decod determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations ...
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... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4275 CY7C4285 /SMODE is tied CC /SMODE is tied to V ...
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... Max. –10 + > –10 + < V < Com’l 50 Ind 55 Com’l 2 Ind 2 Test Conditions ° MHz 5.0V CC CY7C4275 CY7C4285 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C 7C42X5-5 7C42X5-25 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0 ...
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... THÉ VENIN EQUIVALENT 410Ω OUTPUT 7C42X5-10 Min. Max. 100 2 10 4.5 4.5 3 0 [12 [12] 3 [13] /SMODE tied /SMODE tied [13] /SMODE tied OHZ . PAF(E) CY7C4275 CY7C4285 90% 90% 10% 10% ≤ 4275–5 1.91V 7C42X5-15 7C42X5-25 Min. Max. Min. Max. Unit 66.7 40 MHz ...
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... SKEW2 Empty Flag t Skew Time between Read Clock and Write Clock for SKEW3 Programmable Almost Empty and Programmable Al- most Full Flags (Synchronous Mode only) Document #: 38-06008 Rev. *B 7C42X5-10 Min. Max. 8 /SMODE tied 4 CY7C4275 CY7C4285 7C42X5-15 7C42X5-25 Min. Max. Min. Max. Unit 6 ...
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... A VALID DATA t OE [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4275 CY7C4285 NO OPERATION t WFF 4275–6 t REF t OHZ 4275–7 Page ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06008 Rev RSR t RSF t RSF t RSF [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4275 CY7C4285 [17] OE=1 OE=0 4275– [19 4275–9 (maximum) = either 2 FRL CLK SKEW2 CLK SKEW2 Page [+] Feedback ...
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... REN LOW DATA IN OUTPUT REGISTER Q – Document #: 38-06008 Rev ENS REF REF SKEW2 [14 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4275 CY7C4285 t ENH [18] t FRL t REF D0 4275–10 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ 4275–11 Page [+] Feedback ...
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... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06008 Rev CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ENS t CLKL t t ENS ENH t PAE WORDS IN FIFO t PAE t ENS CY7C4275 CY7C4285 HALF FULLOR LESS 4275–12 n WORDS IN FIFO 4275–13 Page [+] Feedback ...
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... PAF offset = m. Number of data words written into FIFO already = 32768 − for the CY7C4285 and 65536 − for the CY7C4285. 25. PAF is offset = m. 26. 32768 − m words in CY7C4275 and 65536 – m words in CY7C4285. 27. 32768 − words in CY7C4275 and 65536 – CY7C4285. Document #: 38-06008 Rev ...
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... PAF may not change state until the next WCLK rising edge. SKEW3 Document #: 38-06008 Rev CLKL Note 28 t ENH Note 29 t PAF FULL– M WORDS IN FIFO t SKEW3 t ENS t CLKL t ENH t DH PAF OFFSET CY7C4275 CY7C4285 [26] t [30] PAF synch t t ENS ENH 4275–16 PAE OFFSET – 4275–17 Page [+] Feedback ...
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... WXI t WCLK Notes: 31. Write to last physical location. 32. Read from last physical location. Document #: 38-06008 Rev CLKL t ENH t A UNKNOWN PAE OFFSET Note Note Note XIS CY7C4275 CY7C4285 PAF OFFSET PAE OFFSET 4275–18 4275–19 4275–20 4275–21 Page [+] Feedback ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06008 Rev XIS t PRT t RTR . RTR to update these flags. RTR CY7C4275 CY7C4285 4275–22 4275–23 Page [+] Feedback ...
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... Architecture The CY7C4275/85 consists of an array of 32K/64K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4275/85 also includes the control signals WXI, RXI, WXO, RXO for depth expansion ...
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... Notes: 37 Empty Offset (Default Values: CY7C4275/CY7C4285 n = 127). 38 Full Offset (Default Values: CY7C4275/CY7C4285 n = 127). Document #: 38-06008 Rev. *B nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse ...
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... Width Expansion Configuration The CY7C4275/85 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- pansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN ( WRITE CLOCK (WCLK) ...
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... Depth Expansion Configuration (with Programmable Flags) The CY7C4275/85 can easily be adapted to applications re- quiring more than 32,768/65,536 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
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... Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Package Name Type A64 64-Lead 10x10 Thin Quad Flatpack Figure 3. 64-PIn TQFP (10X10X1.4 mm) CY7C4275 CY7C4285 Operating Range Commercial 51-85051 *B Page [+] Feedback ...
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... Document Title: CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number: 38-06008 REV. ECN NO. Issue Date ** 106469 07/12/01 *A 122260 12/26/02 *B 2897215 03/22/10 Document #: 38-06008 Rev. *B © Cypress Semiconductor Corporation, 2000-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...