CLA90000 Zarlink Semiconductor, CLA90000 Datasheet

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CLA90000

Manufacturer Part Number
CLA90000
Description
High Density CMOS Gate Arrays
Manufacturer
Zarlink Semiconductor
Datasheet
www.DataSheet4U.com
( DataSheet : www.DataSheet4U.com )
INTRODUCTZarlinkION
The CLA90000 family of gate arrays from Zarlink Semicon-
ductor consists of 14 fixed-size arrays with the option of
building optimized arrays with up to 1.1 million gates. This
family offers low-power, mixed voltage capability and a high
density silicon architecture. The CLA90000 series is easy
to use with and without synthesis tools and comes with
design utilities to provide customers with a faster time to
market.
FEATURES
I Low power, 0.5 µ W/MHz/gate at 3V supply (NAND 2
I High density of 5,425 available gates/mm
I 3V and 5V I/O capability on the same device
I 150ps gate delay for 2-input NAND with two loads (5V)
I Accurate delay modelling for gates and tracks with sign
I CAD libraries optimized for synthesis
I Up to 512K available gates and 352 pads with fixed
I Up to 1.1M available gates and 520 pads with optimized
I Double or triple layer metal on a 0.6 µ m (drawn) process
I Operation from 2.7V to 5.5V
I Methodologies for low clock skew
I Phase locked loop cells, both gate array variant and
I Embedded RAM and ROM
I Expanding range of Zarlink SytemBuilder  soft and
I Wide range of packaging options including Ball Grid
I Commercial and military pad density options
Arrays
loads)
off quality CAE design libraries for QuickSim II and
Verilog-XL
arrays
arrays
embedded variant with on-chip filter
hard cells for complex functions including 85C30, 8051,
and 8251 devices
2
BENEFITS
I Fast Customer Time To Market
I Cost-effective solutions
OVERVIEW
The CLA90000 series product has a number of important
elements that assist designers.
Ease of design
Ease of design is an important feature of this new product,
as shown by the checking and verification utilities built into
the Zarlink design kits. Accurate simulation is essential for
good design, and the Zarlink 5
model algorithms help ensure first time success. Various
design routes and industry-standard systems are avail-
able.
Cell Libraries
Cell libraries are optimized for synthesis and include a
complete range of soft and hard macros. Cells include
basic logic, oscillators, JTAG controllers and macros from
the extensive SystemBuilder™ library such as micropro-
cessors, memories, UARTs, and DSP elements, which
improve time to market through a shorter design cycle.
Embedded custom blocks can be inserted into a gate
array to produce dense memory or other compact high
performance components. Optimized arrays can offer gate
array cycle times if embedded blocks are defined early in
the design cycle.
- Direct sign-off on industry standard CAE tools
- Comprehensive industry-standard design tool flows
- SystemBuilder™ megacell libraries
- Worldwide design centre support
- Reliable prototype and production delivery
- Two silicon sources
- Optimized silicon architecture for excellent silicon
- Statistical process control for optimum yield
- High quality and reliability, manufactured to MIL STD
DS5500
utilization
883 methods and other industry recognized standards
High Density CMOS Gate Arrays
CLA90000 Series
ISSUE 2.0
th
order pin to pin delay
www.DataSheet4U.com
April 1997

Related parts for CLA90000

CLA90000 Summary of contents

Page 1

... DataSheet : www.DataSheet4U.com ) INTRODUCTZarlinkION The CLA90000 family of gate arrays from Zarlink Semicon- ductor consists of 14 fixed-size arrays with the option of building optimized arrays with up to 1.1 million gates. This family offers low-power, mixed voltage capability and a high density silicon architecture. The CLA90000 series is easy ...

Page 2

... The lower pad density meets the need of MIL STD customers in terms of bond wire spacing specifications with utilization for CLA90000 has a range of fixed array bases to offer a suit- able array size for most applications, from low to high vol- ume. Fixed Gate Arrays Array ...

Page 3

... TTL or CMOS compatible input Schmitt circuitry. 3V cells meet both TTL and CMOS spec- ifications. The CLA90000 has four separate internal supply rails: one for the core, one for the buffer, and two for output areas of the chip. The buffer supply rail is completely isolated for very low noise. This offers the benefi ...

Page 4

... Methods of implementation are available for use with flat layout, manual methods, or hierarchy. A sim- plified grid arrangement is shown below. In addition the CLA90000 series of arrays is supported by EPIC Power- Mill  power estimation software (check availability).. Optional horizontal metal-3 grid Local ...

Page 5

... I Flexible design routes I Proven right first time design I Local design support Design and layout support for the CLA90000 arrays is available from many local centres worldwide, each con- nected to our headquarters via high speed data links. A design centre engineer, as part of the Zarlink support ...

Page 6

SOFTWARE TOOLS INDUSTRY STANDARD DESIGN SOFTWARE AND Zarlink LIBRARIES Zarlink VERIFICATION TOOLS Zarlink OR INDUSTRY- STANDARD LAYOUT TOOLS INDUSTRY- STANDARD SOFTWARE 6 Concept Assessment DESIGN REVIEW 1 Design capture/compilation or synthesis Improve testability Testability analysis Correct design errors Functional simulation ...

Page 7

... To meet the requirements of high speed, high gate count designs, Zarlink CLA90000 arrays offer low power factors F and a selection of power packages for improved thermal management. ...

Page 8

DERATING FOR VOLTAGE PROCESS AND TEMPERATURE The following figures show how gate delay increases as supply voltage is reduced. 3 2.5 2 1.5 1 0.5 2.15 2.40 2.65 2.70 3.00 3.30 3.60 4.50 5.00 5.50 Figure 5 Derating for a ...

Page 9

... AC ELECTRICAL CHARACTERISTICS For the CLA90000 series, one load unit (LU) is 17fF. Typical Microcell Delays (ns) (25°C, 0.2ns input edge) Gates (2LU) INVX1 tpLH 0.24 tpHL 0.12 NAND2X2 tpLH 0.18 tpHL 0.15 NOR2x2 tpLH 0.31 tpHL 0.10 SDF tpLH 0.81 tpHL 0.61 Typical I/O Delays (25°C, 0.2ns input edge) I/O delays depend on the voltage of the device, i.e. all 5V I/O, all 3V I/O, or mixed 3V and 5V I/O ...

Page 10

Example delays for mixed 3V and 5V I/O (ns) Delays for mixed 3 and 5V I/O are not the same as for sin- gle voltage designs because of level shifting stages mixed 3V and 5V I/O ...

Page 11

Input Switching Thresholds All characteristics are for temperatures between -55 and 150°C (junction temperature). Characteristic Symbol CMOS Schmitt - CS Input low voltage V Input high voltage V Hysteresis V TTL Schmitt - TS Input low voltage V Input high ...

Page 12

Output Voltages and Currents All characteristics are for temperatures between -55 and 150°C (junction temperature). Characteristic Symbol High output volt- age All outputs V OH 01N V OH 02N V OH 03N V OH 06N V OH 12N V OH ...

Page 13

Short Circuit Currents All characteristics are for temperatures between -55 and 150°C (junction temperature). Characteristic Symbol Output short circuit current 01N I OS 02N I OS 03N I OS 06N I OS 12N I OS Output short circuit current 01N ...

Page 14

... I Oscillator cells I 3.3V and 5V PCI/PC Card cells I JTAG controller (check availability) A comprehensive cell library is available for the CLA90000 series including cells for specific applications. The library is being continually expanded, so please check with your local Zarlink representative for the latest addi- tions ...

Page 15

SystemBuilder Cells Name M85C30 Two channel enhanced Serial Communications Controller (SCC) with FIFOs M82530 Two channel enhanced Serial Communications Controller (SCC) MFDC High performance PC-compatible floppy disk controller (82077SL) with M765A core M765A Extended features floppy disk controller core for ...

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AND Gates Cell Name Cell Function AND2 2-input AND x1drive AND2X2 2-input AND x 2drive AND2X4 2-input AND x4 drive AND3 3-input AND x1 drive AND3X2 3-input AND x2 drive AND3X4 3-input AND x4 drive AND4 4-input AND x1 drive ...

Page 17

AND-OR-INVERTER Gates Cell Name Cell Function A2DO2I 2-2 AOI x1 drive A2DO2IX2 2-2 AOI x2 drive A2O2I 2-1 AOI x1 drive A2O2IX2 2-1 AOI x2 drive A2O3I 2-1-1 AOI x1 drive A2O3IX2 2-1-1 AOI x2 drive A2DO3I 2-2-1 AOI x1 ...

Page 18

Tristate Buffers Cell Cell Function Name BDRX1 Tristate noninv buffer active low enable x1 drive BDRX2 Tristate noninv buffer active low enable x2 drive BDRX4 Tristate noninv buffer active low enable x4 drive BDRX8 Tristate noninv buffer active low enable ...

Page 19

I/O Cells Cell Name 5V Core and 5V I/O ATSIrddN 5V I/O, Schmitt input (TTL) ACSIrddN 5V I/O, Schmitt input (CMOS) Cell Name 3V core and 3V I/O BBSIrddN 3V I/O, Schmitt input (TTL/CMOS) Cell Name 3V core with 3V ...

Page 20

Key to packages, 1234 = Format number of preferred array/qualified package combination. 1234 = Check availability with Zarlink. 1234 ^ = Check prototype package with Zarlink. † development. 1234 * = Maximum number of ceramic prototypes is 10 ...

Page 21

FQFP (Fine pitch) - Plastic Style Leads Code F 100 FQFP100-FP-1414 Q 208 FQFP208-FP-2828 F P Style Leads Code F 100 FQFP100-FP-1414 Q 208 FQFP208-FP-2828 F 240 FQFP240-FP-3232 P 304 FQFP304-FP-4040 LQFP (Low Profile) - Plastic Style Leads Code 48 ...

Page 22

P2QFP ('PowerQuad 2') - Plastic with Copper Heat Slug Style Leads Code 100 P2QFP100-GH-1420 P 120 P2QFP120-GH-2828 2 128 P2QFP128-GH-2828 Q 144 P2QFP144-GH-2828 F 160 P2QFP160-GH-2828 P 208 P2QFP208-GH-2828 Style Leads Code 100 P2QFP100-GH-1420 P 120 P2QFP120-GH-2828 2 128 P2QFP128-GH-2828 ...

Page 23

BGA, Ball Grid Array - Plastic Style Leads Code P 169 PBGA169-BP-2323 B 225 PBGA225-BP-2727 G 313 PBGA313-BP-3535 A 352 PBGA352-BP-3535 Style Leads Code P 169 PBGA169-BP-2323 B 225 PBGA225-BP-2727 G 313 PBGA313-BP-3535 A 352 PBGA352-BP-3535 TQFP (Thin Profile) - ...

Page 24

High Density Pad Array Prototyping Packages Important: CQFP/CBGA packages are intended for prototyping only. Production capability is available in special cases. Prototypes for MQFPs and P2 & P4 MQFPs Style Leads Code 44 CQFP44-GG-1010 52 CQFP52-GG-1010 64 CQFP64- GG-1420 C ...

Page 25

Prototypes for PLCC Style Leads Code C 44 CcLCC44-HC-1717 c 68 CcLCC68-HC-2525 L 84 CcLCC84-HC-3030 C C Prototypes for BGAs Style Leads Code C 169 CBGA169-BC-2323 B 225 CBGA225-BC-2727 G 313 CBGA313-BC-3535 A 352 CBGA352-BC-3535 Style Leads Code C 169 ...

Page 26

Standard Density Pad Array Packages, Military Arrays LdCC Style Leads Code L 132 LdCC132-GCA-2424 d 172 LdCC172-GCA-3030 C 196 LdCC196-GCA-3535 C Style Leads Code L 132 LdCC132-GCA-2424 d 172 LdCC172-GCA-3030 C 196 LdCC196-GCA-3535 C LdCC & TLdCC - Power Style ...

Page 27

PGA Style Leads Code 68 PGA68-ACA-2828 84 PGA84-ACA-2828 P 100 PGA100-ACA-3434 G 120 PGA120-ACA-3434 A 132 PGA132-ACA-3636 144 PGA144-ACA-4040 180 PGA180-ACA-4040 181 PGA181-ACA-4040 257 PGA257-ACA-5151 Style Leads Code 100 PGA100-ACA-3434 120 PGA120-ACA-3434 P 132 PGA132-ACA-3636 G 144 PGA144-ACA-4040 A 180 ...

Page 28

... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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