CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 6

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA200 Series
DESIGN SUPPORT
Zarlink Semiconductor offers fully flexible design support
allowing customer a wide choice of design interfaces.
Whichever design interface is chosen each customer design
is supported full-time by an applications engineer with
software support from the Zarlink Semiconductor group that
produces the design kits. Four main design interfaces are
supported. These are described in table 2 below.
The design process incorporates a design audit procedure to
verify compliance and to ensure manufacturability.
procedure includes three design reviews held at key stages of
the design process to ensure device performance and
timescales.
Design Review 1: Held at the beginning of the design cycle
Design Review 2: Held after logic simulation but prior to
Design Review 3: Held after layout and post layout
6
Interface
1
2
3
4
Description
Netlist interface. Customer completes logical design and simulation using a design kit. Zarlink Semiconductor
performs layout only.
Technology mapping. Zarlink Semiconductor converts a customer-supplied netlist created using a non-
Zarlink Semiconductor library (e.g., FPGA or other vendor’s library) and simulates using customer-supplied
test patterns. The production test program is based on these test patterns. Zarlink Semiconductor performs
layout.
Layout interface. Customer completes logical design and simulation. Customer performs layout.
Turnkey. Zarlink Semiconductor completes schematic capture or logic synthesis or both based on a paper
schematic or specification or VHDL or Verilog description. Zarlink Semiconductor performs layout.
to check and agree on performance,
packaging, specification and design time
scales
layout to ensure satisfactory functionality,
timing performance and adequate fault
coverage
simulation verification of satisfactory
design performance after insertion of
actual track loads. This is the final check
of all device specifications prior to
prototype manufacture
Advance Information
Table. 2 Zaralink Semiconductor Design interfaces
The
CAE SUPPORT
The CLA200 Series is supported with comprehensive design
kits for industry standard design tools
Graphics, Cadence Design Systems, and Synopsys. A VITAL
compliant library is also supported.
Features of design kits include :
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•
•
•
•
•
•
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Use of the design kits for sign-off enable customers to sign-off
their design without the need to re-simulate on a golden
simulator. This has the benefit of customers not having to
learn new tools. There is also no overhead in engineering
effort or time taken rechecking simulation results.
Sign-off simulation with Mentor or Cadence
VITAL sign off with Synopsys VSS
Full top down design flow support
Synthesis with Synopsys, Mentor or Cadence
Electrical Rule Checks (ERC)
Paracell Model Generator (PMG)
VIEWLOGIC VCS simulator supported
Sunrise ATPG supported
Advanced Pin to Pin Delay modelling
Floorplanning with Compass Chipplanner
Direct routes to layout and test
including Mentor