CLA200 Zarlink Semiconductor, CLA200 Datasheet
CLA200
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CLA200 Summary of contents
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... DataSheet : www.DataSheet4U.com ) INTRODUCTION The CLA200 Series Arrays from Zarlink Semiconductor offer designers the capability to integrate designs of more than 2 million gates. There are 14 fixed arrays optimised for low to medium complexity designs ranging from 11K used gates up to 628K used gates. For larger designs optimised arrays can be built with million available gates ...
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... CLA200 Series Advance Information ARRAY ARCHITECTURE The CLA200 Series gate array family is based on a sea of gates array architecture. The arrays consist of a core of transistors, overlaid with a core power supply grid, ringed by three concentric pairs of VDD and GND supply rail. The OPVDD rail can be split to form an extra VDD rail named split supply VDD (SSVDD) to allow mixed voltages interfaces on the same device ...
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... I/O cell. 24mA current drive available using two output cells The CLA200 has four separate VDD supply rails and two GND rails, one VDD rail for the core, one for input buffers, and two for output areas of the chip. The intermediate buffer supply rail can be completely isolated for very low noise ...
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... Figure 2 illustrates the layout of each buffer 256 Words stage, which is done automatically at layout. 64 Bits Power Distribution CLA200 can be used from 1.8 to 3.3V, giving great flexibility 9 supply voltage. Core supply can be chosen from a nominal 6 3.3V, with mixed voltage I/O available if the core supply is 2V ...
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... CMOS processes results in a corresponding increase in power dissipation. Designs can now have more than half a million used gates and chip power consumption is an important issue. The CLA200 series offers the following: • Lower power CMOS for improved thermal management • ...
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... VHDL or Verilog description. Zarlink Semiconductor performs layout. Table. 2 Zaralink Semiconductor Design interfaces 6 CAE SUPPORT The CLA200 Series is supported with comprehensive design kits for industry standard design tools Graphics, Cadence Design Systems, and Synopsys. A VITAL compliant library is also supported. Features of design kits include : • ...
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... -12 -24 - 1.48 V 0.3 VDD 0.7 VDD 0.8 V 2.0 V 1.2 V 1.6 V CLA200 Series Parameter Min Max 1.8 3.6 4.5 5.5 0.0 VDD 0.0 VBIAS 0.0 VDD - 30 -55 150 0 70 -40 85 -55 125 VDD = 3.6V No Pull Up/Down Cells No Pull Up/Down Cells Not including package Not including package Not including package 3.0V < ...
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... CLA200 Series Advance Information CMOS and TTL Output Levels All characteristics are over all process conditions from -40 to +85 C Parameter Vol CMOS Voh Vol TTL Voh Note: These figures apply for all Output Current Conditions shown below Output Currents Device Voltage 1.8V < ...
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... Temperature MANUFACTURING The CLA200 Series product is manufactured in Zarlink Semiconductor advanced wafer fabrication facility near Plymouth, England. This facility is a purpose-built, vibration- free facility equipped with the latest automated technology for 8 inch wafer processing. This equipment utilises mini- environments together with the use of SMIF boxes to achieve ultra clean processing conditions ...
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... CLA200 Series Advance Information PACKAGING The CLA200 Series is available in a wide range of metric quad flat packages (MQFP) and plastic ball grid array packages (BGA) . The currently supported Die size and Package combinations are shaded. The package style and pin count information is intended only as a guide. Detailed package ...
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... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...