HMP9701 Intersil Corporation, HMP9701 Datasheet - Page 8

• Manufacturer Part Number: HMP9701
• Description: AC97 Audio Codec
• Manufacturer: Intersil Corporation

Testability
The HMP9701 provides a test mode to support the in circuit
test capabilities provided by automatic test equipment (ATE).
In this mode, the HMP9701 drives its digital AC-Link outputs
(BIT_CLK and SDATA_IN) to a high impedance state. This
allows for in circuit testing of the digital controller component
of the sound subsystem.
The HMP9701 enters ATE test mode when SDATA_OUT is
sampled high by the trailing edge of RESET (see AC Timing
Diagrams). The HMP9701 will remain in test mode until a
“cold” reset returns the part to normal operation.
Control/Status Registers
The HMP9701 contains a bank of 16-bit control/status regis-
ters to control and monitor part operation. The control regis-
ters are accessed via the even addresses within the 6-bit
address space provided in Slot 1 of the Audio Output Frame.
The control/status register address map is given in Table 20.
Reset Register (Index 00h)
Writing any value to this register performs a register reset
that causes all registers to revert to their default values.
Reading this register returns the AC’97 ID code that
specifies the optional AC’97 features supported by the
HMP9701. This register will read back 0001h to indicate that
the HMP9701 provides the optional ADC for a dedicated
MIC channel.
Master Volume Control Registers (Index 02h, 06h)
These registers manage the output audio volumes. Register
02h sets the master stereo volume (LINE_OUT_L,
LINE_OUT_R) and Register 06h controls the mono volume
(MONO_OUT). Each volume step corresponds to 1.5dB.
The MSB of both registers is the mute bit. When this bit is
set to 1 the level for that channel is set at - dB.
The HMP9701 supports 5 bits of gain control for the stereo
line out and mono out. The right and left stereo channels are
controlled via MR4:0 and ML4:0 respectively. The mono out-
put is controlled by MM4:0. Writing a “1” to MR5, ML5, or
MM5 will force the volume level to max attenuation, Mx4:0 =
11111 (46.5dB attenuation). Note: if these registers are writ-
ten with Mx5:0 = 1xxxx, they will read back Mx5:0 = 01111.
Default Value: 8000h (0dB Gain with Mute On)
MUTE
0
0
0
1
TABLE 11. MASTER VOLUME SETTINGS
MX5...MX0
00 0000
01 1111
1x xxxx
xx xxxx
0dB Attenuation
46.5dB Attenuation
46.5dB Attenuation
- dB Attenuation
FUNCTION
HMP9701
8
PC Beep Register (Index 0Ah)
This register controls the level of the PC Beep input. The PC
Beep is attenuated as specified by the contents of this regis-
ter and mixed equally into both the right and left output chan-
nels. The PC_BEEP input is attenuated in 3dB steps from
0dB to 45dB. The MSB of the register is the mute bit. When
this bit is set to 1 the level for that channel is set at -
Input Volume Control (Index 0Ch- 18h)
These registers control the input gain/attenuate/mute (GAM)
blocks through which each of the analog mixer’s inputs pass.
Each GAM block has a 5-bit control that supports setting the
gain in increments of 1.5dB. A total gain range from +12dB to
-34.5dB is supported. The MSB of each register is a Mute bit
that will set the gain to - dB when programmed to 1. Note: reg-
ister 0Eh (Mic Volume Register) has an extra bit that is for a
20dB boost. When bit 6 is set to 1 the 20dB boost is on.
Record Select (Index 1Ah)
This register is used to select the record source for the left
and right record ADC’s. The selections are summarized
below in Table 14 and 15.
Default Value: 8000h (0dB Gain w/ Mute on)
Default: All GAM blocks set to Mute with 0dB Gain (see Table 20)
Default: 000 (MIC in)
MUTE
MUTE
0
0
1
0
0
0
1
SR2:0
TABLE 13. ANALOG MIXER INPUT GAIN SETTINGS
TABLE 12. PC_BEEP ATTENUATION SETTINGS
TABLE 14. RECORD SELECT RIGHT CHANNEL
0
1
2
3
4
5
6
7
PV3:0
PV3:0
00000
01000
11111
0000
1111
xxxx
xxxx
RIGHT RECORD SOURCE
0dB Attenuation
45dB Attenuation
+12dB Gain
0dB Gain
-34.5dB Gain
- dB Attenuation
-
Stereo Mix Right
dB Gain
LINE_IN_R
VIDEO_R
Mono Mix
PHONE
AUX_R
CD_R
MIC
FUNCTION
FUNCTION
dB.