HMP9701 Intersil Corporation, HMP9701 Datasheet
HMP9701
Related parts for HMP9701
HMP9701 Summary of contents
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... HMP9701 helps pave the way for PC’97 com- pliant desktop, portable and entertainment PCs with a cost effective high-quality audio solution. As the analog front end of the AC’97 chipset, the HMP9701 accepts line level audio inputs from seven different sources and converts the analog audio to 16-bit digital streams of either ste- reo or mono data. The 48 Kss data is transmitted to the control- ler via the AC’ ...
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... PC_BEEP STEREO SIGNAL PATH MONO SIGNAL PATH Functional Description The HMP9701 is a full-duplex stereo audio codec compliant to the AC’97 Codec specification. This component is designed for use in multimedia and business personal computers. The codec includes full duplex stereo converters, a mic pass through ADC, complete on-chip anti-alias fi ...
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... CONTROLLER FIGURE 1. HMP9701 CONNECTION TO AC’97 CONTROLLER Digital Serial Interface (AC Link) The HMP9701 is linked to an AC’97 digital controller via a 5 pin digital serial interface as shown in Figure 1. This inter- face, the AC-link, supports bidirectional, fixed rate, serial data streams. The data transfers are based on a time divi- ...
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... The first bit of the output audio frame (Slot 0, bit 15) flags the validity of the entire audio frame. If the “Valid Frame” bit this indicates that the current audio frame contains at least one time slot of valid data. The HMP9701 monitors the next 4 bit positions to determine whether the data in the con- HMP9701 20 ...
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... The first bit of an input audio frame (Slot 0, bit 15) indicates whether the HMP970’s AC Link is functional. If the “Codec Ready” bit the HMP9701 is not ready for normal oper- COMMENT ation. If the “Codec Ready” bit is “1”, the HMP9701 is ready to perform control and status register transfers ...
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... The state of pow- erdown is controlled by the Powerdown Register (26h). This register provides 6 commands to powerdown various sections of the HMP9701. A summary of the power down commands is given in Table 10 with a more complete description given in the Control Register Section. Note, the HMP9701 is a fully static design which will preserve the contents of the internal control registers if the internal clock is stopped ...
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... By driving RESET low, BIT_CLK will be activated, the AC-Link will return to normal operation, and all HMP9701 control registers will be initialized to their default values. RESET is an asynchronous HMP9701 input. Note: the HMP9701 HMP9701 will remain in the reset state as long as RESET is asserted “low”. Suggested Powerdown Sequences PR0= 1 ADCs ...
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... Testability The HMP9701 provides a test mode to support the in circuit test capabilities provided by automatic test equipment (ATE). In this mode, the HMP9701 drives its digital AC-Link outputs (BIT_CLK and SDATA_IN high impedance state. This allows for in circuit testing of the digital controller component of the sound subsystem ...
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... Internal Clock Disable (1 = CLK Off CLK On) Default: na The lower byte of this register is used to monitor the status of individual sections with in the HMP9701. The status bits, as summarized in Table 19, indicate whether a subsection is in it’s normal operational state (Ready). Note: the status bits are read only, and writes to this register will have no effect on the state of these bits ...
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REG NAME D15 D14 D13 00h Reset 02h Master Volume Mute X ML5 04h Reserved 06h Master Volume Mono Mute X X 08h Reserved 0Ah PC_BEEP Volume Mute X X 0Ch ...
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... NAME NUMBER OUTPUT DIGITAL I/O RESET 11 I RESET - This active low signal causes a HMP9701 hardware reset that will return the control/status registers to their default conditions. SYNC 10 I SYNC - 48kHz sync pulse which defines the beginning of serial audio I/O frames. Note: must be synchronous to BIT_CLK. ...
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... Crystal Input. Leave this pin unconnected when using an external clock source. XTL_OUT 3 O 24.576MHz Crystal Output. This pin may also be used to input an external 24.576MHz clock source Analog Supply Voltage (5.0V). AA AGND 26 Analog Ground Digital Supply Voltage (5.0V). DD GND Digital Ground. HMP9701 DESCRIPTION 12 ...
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... Operating Conditions Temperature Range HMP9701CN CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... BCP t Note 3 BCH t Note 3 BCL Note CRL t R2BC t SRH t S2BC t PDWN t SU2RST t Note 3 HZ MIN TYP 0 - 0.4xFs - - - 0.6xFs - HMP9701CN MIN TYP MAX UNITS - 12.288 - MHz - 81 32.56 - 48.84 ns 32.56 - 48. kHz - 20 BCP - 240 * BCP ...
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... Total Out of Band Energy (28.8kHz - 100kHz) Mute Attenuation (0dB) Audible Out of Band Energy (20kHz - 28.8kHz) Deviation from Linear Phase Programmable Attenuation/Gain PARAMETER Record Gain (0dB to 22.5dB) Record Gain Step Size PCM Output Volume Span (+12dB to -34.5dB) PCM Output Volume Span Step Size HMP9701 MIN TYP - ...
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... Based on 1kHz, Full scale analog tone input; Measurement Bandwidth 20kHz, A-weighted. 5. DAC’s driven with 1kHz, Full Scale PCM Sine Wave, output measurement bandwidth 20kHz, A-weighted. 6. Test performed with C = 40pF 4mA This is measured relative to a nominal output level. HMP9701 (Note 2) (Continued) MIN TYP - 2.83 10 ...
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... FREQUENCY (xF FIGURE 12. ANALOG-TO-DIGITAL TRANSITION BAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB) 0.05 0 -0.05 -0.10 -0.15 -0.20 FREQUENCY (xF FIGURE 14. DIGITAL-TO-ANALOG PASSBAND FREQUENCY RESPONSE (FULL SCALE INPUTS, 0dB) HMP9701 ADC/DAC Frequency Responses 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -0 FIGURE 11. ANALOG-TO-DIGITAL PASSBAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB) ...
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... SRH SYNC BIT_CLK FIGURE 18. WARM RESET TIMING t t BCH BIT_CLK t SH SYNC FIGURE 20. CLOCKS BIT_CLK SDATA_IN SDATA_OUT SYNC HMP9701 RESET SDATA_OUT BIT_CLK, SDATA_IN BIT_CLK, SDATA_IN FIGURE 19. RISE AND FALL TIMES BCL BIT_CLK SDATA_IN SLOT SDATA_OUT SLOT 12 NOTE: BCLK not to scale. ...
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... F 0 PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L 42 19 AGND HMP9701 CD_GND CD_R 40 21 CAP4 MIC1 39 22 CAP3 MIC2 LINE_IN_L 37 24 MONO_OUT LINE_IN_R 0.1 F 1.0 F CERAMIC + 0 1nF (NP0) 1nF (NP0) 1nF (NP0) ...
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... Locate all decoupling capacitors CLOSE to their associat- ed pins on the codec. 5. Please note that all analog inputs and outputs of the HMP9701 codec are at the DC level coupling to zero biased signal sources and destina- tions. 6. Keep all analog input and output traces as short as possi- ble, prevent any coupling from adjacent digital lines ...