MT18VDDT6472G-265 Micron, MT18VDDT6472G-265 Datasheet - Page 31
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MT18VDDT6472G-265
Manufacturer Part Number
MT18VDDT6472G-265
Description
512MB DDR SDRAM RDIMM
Manufacturer
Micron
Datasheet
1.MT18VDDT6472G-265.pdf
(39 pages)
- Current page: 31 of 39
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Table 19: EEPROM Device Select Code
The most significant bit (b7) is sent first
Table 20: EEPROM Operating Modes
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
SDA OUT
SELECT CODE
MODE
Memory Area Select Code (two arrays)
Protection Register Select Code
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
SDA IN
SCL
t SU:STA
Figure 16: SPD EEPROM Timing Diagram
RW BIT
1
0
1
1
0
0
t F
t HD:STA
t LOW
t AA
V
V
V
V
IH
IH
IH
IH
WC
V
V
or V
or V
or V
or V
IL
IL
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
b7
IL
IL
IL
IL
t HIGH
1
0
DEVICE TYPE IDENTIFIER
t HD:DAT
BYTES
31
1
1
1
1
16
1
b6
0
1
t DH
INITIAL SEQUENCE
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
t R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
b5
1
1
t SU:DAT
b4
0
0
SA2
SA2
b3
CHIP ENABLE
©2004 Micron Technology, Inc. All rights reserved.
SA1
SA1
b2
t SU:STO
t BUF
SA0
SA0
b1
UNDEFINED
RW
RW
RW
b0
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