MT18LDT1672 Micron, MT18LDT1672 Datasheet - Page 23
![no-image](/images/no-image-200.jpg)
MT18LDT1672
Manufacturer Part Number
MT18LDT1672
Description
168-Pin DRAM DIMMs (x72) Buffered
Manufacturer
Micron
Datasheet
1.MT18LDT1672.pdf
(28 pages)
- Current page: 23 of 28
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TIMING PARAMETERS
NOTE: A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
AA
AR
ASC
ASR
CAC
CAH
CHR
CLZ
CRP
OD
OE
ADDR
RAS#
CAS#
DQ
V
V
IOH
IOL
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
MIN
36
13
10
2
5
6
2
0
t CRP
-5
t ASR
MAX
ROW
30
18
12
12
t RAH
MIN
OPEN
t AR
t RAD
43
15
10
2
5
8
2
0
t RCD
-6
(WE# = HIGH; OE# = LOW)
MAX
HIDDEN REFRESH CYCLE
35
20
15
15
t ASC
t RC
t RAS
COLUMN
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t CAH
t AA
t RAC
t CAC
t CLZ
t RSH
23
t RP
SYMBOL
t
t
t
t
t
t
t
t
t
t
OFF
ORD
RAC
RAD
RAH
RAS
RC
RCD
RP
RSH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BUFFERED DRAM DIMMs
MIN
50
84
30
18
2
0
7
7
9
VALID DATA
t RAS
t CHR
-5
8, 16, 32 MEG x 72
10,000
MAX
17
50
MIN
104
10
60
12
40
20
2
0
8
-6
©2000, Micron Technology, Inc.
DON’T CARE
UNDEFINED
t OFF
10,000
MAX
20
60
OPEN
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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