MT16LSDT3264 Micron, MT16LSDT3264 Datasheet - Page 2

• Manufacturer Part Number: MT16LSDT3264
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

GENERAL DESCRIPTION
high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in a x64 con-
figuration. These modules use internally configured
quad-bank SDRAMs with a synchronous interface (all
signals are registered on the positive edge of the clock
signals CK0-CK3).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed (BA0,
BA1 select the device bank, A0-A11 select the device
row). The address bits registered coincident with the
READ or WRITE command are used to select the start-
ing column location for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An AUTO
PRECHARGE function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst sequence.
ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while
accessing one of the other three device banks will hide
16, 32 Meg x 64 SDRAM DIMMs
SD8_16C16_32X64AG_C.p65 – Rev. C, Pub. 9/01
PIN ASSIGNMENT (168-PIN DIMM FRONT)
PIN SYMBOL PIN SYMBOL PIN
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
The MT8LSDT1664A and MT16LSDT3264A are
Read and write accesses to the SDRAM modules are
The modules provide for programmable READ or
The modules use an internal pipelined architec-
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
V
V
V
V
NC
DD
DD
SS
SS
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQMB0
DQMB1
WE#
CKO
A10
BA1
V
V
V
S0#
NC
V
NC
NC
NC
V
A0
A2
A4
A6
A8
DD
DD
DD
SS
SS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
SYMBOL
DQMB2
DQMB3
DQ16
DQ17
DQ18
DQ19
DQ20
CKE1
V
V
V
NC
S2#
NC
NC
NC
NC
NC
V
NC
NC
DD
DD
SS
SS
PIN
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
SDA
CK2
V
SCL
V
V
V
V
NC
WP
DD
DD
SS
SS
SS
2
the precharge cycles and provide seamless, high-
speed, random-access operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access. For
more information regarding SDRAM operation, refer to
the 128Mb SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s
SCL (clock) and SDA (data) signals, together with
SA(2:0), which provide eight unique DIMM/EEPROM
addresses.
PIN ASSIGNMENT (168-Pin DIMM BACK)
PIN SYMBOL PIN SYMBOL PIN
100
101
102
103
104
105
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
The modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in
These modules incorporate serial presence-detect
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
V
V
V
V
NC
DD
DD
SS
SS
106
107
108
109
110
111
112 DQMB4
113 DQMB5
114
115
116
117
118
119
120
121
122
123
124
125
126
168-PIN SDRAM DIMMs
128MB / 256MB (x64)
CAS#
RAS#
BA0
V
A11
V
CK1
S1#
NC
V
NC
NC
V
NC
A1
A3
A5
A7
A9
DD
DD
SS
SS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
SYMBOL
DQMB6
DQMB7
DQ48
DQ49
DQ50
DQ51
DQ52
CKE0
V
V
S3#
V
NC
NC
NC
NC
NC
V
NC
NC
NC
DD
DD
SS
SS
©2001, Micron Technology, Inc.
PIN
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CK3
SA0
SA1
SA2
V
V
V
V
V
NC
DD
DD
SS
SS
SS