MT16LSDT1664AG-133B1 Micron, MT16LSDT1664AG-133B1 Datasheet - Page 9

• Manufacturer Part Number: MT16LSDT1664AG-133B1
• Description: DRAM Module, 64MB (x64, SR), 128MB (x64, DR) 168-PIN SDRAM UDIMM
• Manufacturer: Micron

MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Mode Register Definition Diagram.
burst length determines the maximum number of col-
umn locations that can be accessed for a given READ
or WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1–
A8 when the burst length is set to two; by A2–A8 when
the burst length is set to four; and by A3–A8 when the
burst length is set to eight. The remaining (least signif-
icant) address bit(s) is (are) used to select the starting
location within the block.
within the page if the boundary is reached, as shown in
the Burst Definition Table.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
The mode register is programmed via the LOAD
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
Full-page bursts wrap
The
9
64MB (x64, SR), 128MB (x64, DR)
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
to ensure compatibility
with future devices.
M11, M10 = “0, 0”
*Should program
The ordering of accesses within a burst is deter-
The CAS latency is the delay, in clock cycles,
Figure 5: Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved* WB
11
A11
10
A10
M9
0
1
168-PIN SDRAM UDIMM
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
Diagram
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
BT
M3
Defined
0
1
M6-M0
3
A3
-
M6
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M5
A2
M1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
©2004 Micron Technology, Inc.
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Burst Length
Address Bus
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8