MT16LSDT12864AG-133B1 Micron, MT16LSDT12864AG-133B1 Datasheet - Page 8

• Manufacturer Part Number: MT16LSDT12864AG-133B1
• Description: DRAM Module, 512MB/1GB (x64), 168-PIN SDRAM DIMM
• Manufacturer: Micron

MAND INHIBIT or NOP . Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register Definition
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 5, Mode Register Definition
Diagram, on page 8. The mode register is programmed
via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed
again or the device loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 5 on page 8. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with
the BURST TERMINATE command to generate arbi-
trary burst lengths.
64,128 Meg x 64 SDRAM DIMMs
SD8_16C64_128x64AG_A.fm - Rev. A 11/02 EN
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO REFRESH cycles
The mode register is used to define the specific
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Figure 5: Mode Register Definition
8
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1–
A9, A11 when the burst length is set to two; A2–A9, A11
when the burst length is set to four; and by A3–A9, A11
when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select
the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached, as
shown in Table 7, Burst Definition Table, on page 9.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type, and the
starting column adress, as shown in Table 7, Burst Def-
inition Table, on page 9.
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of the accesses within a burst is deter-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM DIMMs
512MB / 1GB (x64)
©2002, Micron Technology Inc.
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