LM3311SQ National Semiconductor Corporation, LM3311SQ Datasheet - Page 19

• Manufacturer Part Number: LM3311SQ
• Description: Step-up Pwm Dc/dc Converter With Integrated Ldo, Op-amp, And Gate Pulse Modulation Switch
• Manufacturer: National Semiconductor Corporation

the op-amp. The current from the power pins goes through
the output pin and into the load and feedback loop. The cur-
rent exiting the load and feedback loops then must have a
return path back to the op-amp power supply pins. Ideally this
return path must follow the same path as the output pin trace
to the load. Any deviation that makes the loop area larger be-
tween the output current path and the return current path adds
to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to pro-
vide a modulated voltage to the gate driver circuitry of a TFT
LCD display. Operation is best understood by referring to the
GPM block diagram in the Block Diagrams section, the draw-
ing in Figure 2 and the transient waveforms in Figure 3 and
Figure 4.
There are two control signals in the GPM block, VDPM and
VFLK. VDPM is the enable pin for the GPM block. If VDPM is
When VFLK is low, the NMOS switch N3 is turned off which
allows current to charge the C
lay, t
When the voltage on CE reaches about 1.265V and the VFLK
signal is low, the PMOS switch P2 will turn off and the PMOS
switch P3 will turn on connecting resistor R3 to the VGHM pin
through P3. This will discharge the voltage at VGHM at some
rate determined by R3 creating a slope, M
ure 2. The VGHM pin is no longer a current source, it is now
sinking current from the gate drive circuitry.
DELAY
, given by the following equations:
t
DELAY
≊
1.265V(C
E
capacitor. This creates a de-
E
+ 15pF)/I
R
, as shown in Fig-
CE
FIGURE 2.
19
high, the GPM block is active and will respond to the VFLK
drive signal from the timing controller. However, if VDPM is
low, the GPM block will be disabled and both PMOS switches
P2 and P3 will be turned off. The VGHM node will be dis-
charged through a 1kΩ resistor and the NMOS switch N2.
When VDPM is high, typical waveforms for the GPM block
can be seen in Figure 2. The pin VGH is typically driven by a
2x or 3x charge pump. In most cases, the 2x or 3x charge
pump is a discrete solution driven from the SW pin and the
output of the boost switching regulator. When VFLK is high,
the PMOS switch P2 is turned on and the PMOS switch P3 is
turned off. With P2 on, the VGHM pin is pulled to the same
voltage applied to the VGH pin. This provides a high gate drive
voltage, VGHM
circuitry. When VFLK is high, NMOS switch N3 is on which
discharges the capacitor CE.
As VGHM is discharged through R3, the comparator con-
nected to the pin V
switch P3 will turn off when the following is true:
where V
pin V
switching regulator. When PMOS switch P3 turns off, VGHM
will be high impedance until the VFLK pin is high again.
Figure 3 and Figure 4 give typical transient waveforms for the
GPM block. Waveform (1) is the VGHM pin, (2) is the VFLK
and (3) is the VDPM. The output of the boost switching reg-
ulator is operating at 8.5V and there is a 3x discrete charge
pump (~23.5V) supplying the VGH pin. In Figure 3 and Figure
DD
. V
X
is some voltage connected to the resistor divider on
X
is typically connected to the output of the boost
VGHM
MAX
, and can source current to the gate drive
DD
MIN
monitors the VGHM voltage. PMOS
≊
10V
X
R2/(R1 + R2)
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