LM3S3759 Luminary Micro, Inc, LM3S3759 Datasheet - Page 506

• Manufacturer Part Number: LM3S3759
• Description: Lm3s3759 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.3.2
17.4
Table 17-1. Univeral Serial Bus (USB) Controller Register Map
506
Offset
0x000
0x001
0x002
0x004
0x006
0x008
0x00A
Name
USBFADDR
USBPOWER
USBTXIS
USBRXIS
USBTXIE
USBRXIE
USBIS
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
controller. The controller also provides interrupts on device insertion and removal to allow the host
controller code to respond to these external events.
Endpoint Configuration
In order to start communication on host or device mode, the endpoint registers must first be
configured. In Host mode, this provides a connection between an endpoint register and an endpoint
on a device. In Device mode, this provides the setup for a given endpoint before enumerating to
the host controller.
In both cases, the endpoint 0 configuration is limited as this is a fixed function, fixed FIFO size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 bytes with the first 64 bytes in use by endpoint
0. The endpoint’s FIFO does not have to be the same size as the maximum packet size in all cases
as the controller can automatically split for bulk transactions if the FIFO is larger than the maximum
packet size. The FIFO can also be configured as a double-buffered FIFO so that interrupts occur
at the end of each packet and allow filling the other half of the FIFO.
If operating as a device, the USB device controllers' soft connect should be enabled when the device
is ready to start communications. This indicates to the host controller that the device is ready to
start the enumeration process. If operating as a host controller, the device soft connect should be
disabled and power should be provided to VBUS via the USB0EPEN signal.
Register Map
Table 17-1 on page 506 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000.
Type
R/W
R/W
R/W
R/W
RO
RO
RO
0x000E
0x0000
0x0000
0x000F
Reset
0x00
0x20
0x00
Preliminary
Description
USB Device Functional Address
USB Power
USB Transmit Interrupt Status
USB Receive Interrupt Status
USB Transmit Interrupt Enable
USB Receive Interrupt Enable
USB General Interrupt Status
June 02, 2008
page
See
510
511
513
514
515
516
517