LM3S3759 Luminary Micro, Inc, LM3S3759 Datasheet - Page 504

• Manufacturer Part Number: LM3S3759
• Description: Lm3s3759 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.2.3
17.2.3.1 Starting a Session
17.2.3.2 Detecting Activity
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generated. The speed of the device that has been connected can be determined by reading the
USBDEVCTL register where the FSDEV bit is High for a full-speed device and the LSDEV bit is High
for a low-speed device. The USB controller should generate a reset to the device and then the USB
host controller can begin device enumeration. If the device is disconnected while a session is in
progress, a disconnect interrupt is generated.
OTG Mode
In order to conserve power, the USB On-The-Go (OTG) supplement allows VBus to only be powered
up when required and to be turned off when the bus is not in use. VBus is always supplied by the
A device on the bus. The USB OTG controller determines whether it is the A device or the B device
by sampling the ID input from the PHY. This signal is pulled Low when an A-type plug is sensed
(signifying that the USB OTG controller should act as the A device) but taken High when a B-type
plug is sensed (signifying that the USB controller is a B device).
When the USB OTG controller needs to start a session, the SESSION bit should be set in the
USBDEVCTL register. The USB OTG controller then enables ID pin sensing. The ID input is either
taken Low if an A-type connection is detected or High if a B-type connection is detected. The DEV
bit in the USBDEVCTL register is also set to indicate whether the USB OTG controller has adopted
the role of the A device or the B device.
If the USB OTG controller is the A device, then the USB OTG controller enters Host mode (the A
device is always the default host), turns on VBus, and waits for VBus to go above the VBus Valid
threshold, as indicated by the VBUS bit in the USBDEVCTL register going to 0x3. The USB OTG
controller then waits for a peripheral to be connected. When a peripheral is detected, a Connect
interrupt is signaled and either the FSDEV or LSDEV bit in the USBDEVCTL register is set, depending
whether a full-speed or a low-speed peripheral is detected. The USB controller then issues a reset
to the connected device. The SESSION bit in the USBDEVCTL register is cleared to end a session.
The USB OTG controller will also automatically end the session if babble is detected.
If the USB OTG controller is the B device, then the USB OTG controller requests a session using
the Session Request Protocol defined in the USB On-The-Go supplement, that is, it will first discharge
VBus. Then when VBus has gone below the Session End threshold (VBUS bit in the USBDEVCTL
register goes to 0x0) and the line state has been a single-ended zero for > 2 ms, the USB OTG
controller pulses the data line, then pulses VBus. At the end of the session, the SESSION bit is
cleared either by the USB OTG controller or by the application software. The USB OTG controller
then causes the PHY to switch out the pull-up resistor on D+. This signals the A device to end the
session.
When the other device of the OTG set-up wishes to start a session, it either raises VBus above the
Session Valid threshold if it is the A device, or if it is the B device, it pulses the data line then pulses
VBus. Depending on which of these actions happens, the USB controller can determine whether it
is the A device or the B device in the current set-up and act accordingly. If VBus is raised above
the Session Valid threshold, then the USB controller is the B device. The USB controller sets the
SESSION bit in the USBDEVCTL register. When Reset signaling is detected on the bus, a Reset
interrupt is signaled, which is interpreted as the start of a session.
The USB controller is in device mode at this point as the B device is the default mode. At the end
of the session, the A device turns off the power to VBus. When VBus drops below the Session Valid
threshold, the USB controller detects this and clears the SESSION bit to indicate that the session
has ended. This causes a disconnect interrupt to be signaled. If data line and VBus pulsing is
Preliminary
June 02, 2008